Arm64: check matching operands for predicated B16B16 insns

Except for bfml{a,s} their 1st and 3rd operands need to match - pass
the TIED macro argument accordingly. While doing that also slightly
re-arrange table entries, such that all predicated insns are close
together.

At the same time change the existing test source to actually use non-
matching operands for the respective bfml{a,s} forms.

2 files changed, 17 insertions, 17 deletions

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 0ef8b5b..0c7bcf4 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -32211,14 +32211,14 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
     case 1705: return NULL;		/* ldff1h --> NULL.  */
     case 1659: value = 3313; break;	/* ld2h --> ld2q.  */
     case 3313: return NULL;		/* ld2q --> NULL.  */
-    case 2464: value = 3279; break;	/* fclamp --> bfclamp.  */
-    case 3279: return NULL;		/* bfclamp --> NULL.  */
+    case 2464: value = 3281; break;	/* fclamp --> bfclamp.  */
+    case 3281: return NULL;		/* bfclamp --> NULL.  */
     case 1778: value = 1779; break;	/* ldr --> ldr.  */
     case 1779: return NULL;		/* ldr --> NULL.  */
-    case 1434: value = 3278; break;	/* fadd --> bfadd.  */
-    case 3278: return NULL;		/* bfadd --> NULL.  */
-    case 1501: value = 3281; break;	/* fmul --> bfmul.  */
-    case 3281: return NULL;		/* bfmul --> NULL.  */
+    case 1434: value = 3280; break;	/* fadd --> bfadd.  */
+    case 3280: return NULL;		/* bfadd --> NULL.  */
+    case 1501: value = 3282; break;	/* fmul --> bfmul.  */
+    case 3282: return NULL;		/* bfmul --> NULL.  */
     case 1527: value = 3283; break;	/* fsub --> bfsub.  */
     case 3283: return NULL;		/* bfsub --> NULL.  */
     case 1492: value = 3276; break;	/* fmla --> bfmla.  */
@@ -32251,12 +32251,12 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
     case 3271: return NULL;		/* bfadd --> NULL.  */
     case 1482: value = 3273; break;	/* fmaxnm --> bfmaxnm.  */
     case 3273: return NULL;		/* bfmaxnm --> NULL.  */
-    case 1502: value = 3280; break;	/* fmul --> bfmul.  */
-    case 3280: return NULL;		/* bfmul --> NULL.  */
+    case 1502: value = 3278; break;	/* fmul --> bfmul.  */
+    case 3278: return NULL;		/* bfmul --> NULL.  */
     case 1480: value = 3272; break;	/* fmax --> bfmax.  */
     case 3272: return NULL;		/* bfmax --> NULL.  */
-    case 1528: value = 3282; break;	/* fsub --> bfsub.  */
-    case 3282: return NULL;		/* bfsub --> NULL.  */
+    case 1528: value = 3279; break;	/* fsub --> bfsub.  */
+    case 3279: return NULL;		/* bfsub --> NULL.  */
     case 1488: value = 3275; break;	/* fminnm --> bfminnm.  */
     case 3275: return NULL;		/* bfminnm --> NULL.  */
     case 1486: value = 3274; break;	/* fmin --> bfmin.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 4b0b5fd..cea759d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6331,18 +6331,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
 
 /* BFloat16 SVE Instructions.  */
-  B16B16_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
+  B16B16_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
   B16B16_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
   B16B16_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
+  B16B16_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
   B16B16_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
   B16B16_INSN("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
   B16B16_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
   B16B16_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
   B16B16_INSN("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
   B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),