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authorAndrew Waterman <andrew@sifive.com>2017-02-14 15:37:04 -0800
committerPalmer Dabbelt <palmer@dabbelt.com>2017-02-15 10:35:00 -0800
commitf98d33be3af3a8d788aaef37e8fef167b59c81b2 (patch)
tree28419e3c63df6a77c11f96994b864d12feb9cf0e /opcodes
parent773fb663445646ebe45298e255d263f9520b2e2e (diff)
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Add SFENCE.VMA instruction
include/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define. (MASK_SFENCE_VMA): Likewise. (sfence_vma): Declare instruction. opcodes/ChangeLog: 2017-02-14 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and pseudoinstructions.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/riscv-opc.c3
2 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4e58d6c..8830698 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-02-14 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
+ pseudoinstructions.
+
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index cc39390..61d0159 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -678,6 +678,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 },
{"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
{"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
+{"sfence.vma","I", "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS },
+{"sfence.vma","I", "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS },
+{"sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
/* Terminate the list. */