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| author | Jan Beulich <jbeulich@suse.com> | 2023-11-24 09:53:55 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-11-24 09:53:55 +0100 |
| commit | eb5e952f95423bc6ae18457ccc359c8b6c0fa387 (patch) | |
| tree | 994586ba8306938b1ce354c07585987ef5d3dec0 /opcodes | |
| parent | 27b33966b18ed8bf1701a60999448224b1d28273 (diff) | |
| download | gdb-eb5e952f95423bc6ae18457ccc359c8b6c0fa387.zip gdb-eb5e952f95423bc6ae18457ccc359c8b6c0fa387.tar.gz gdb-eb5e952f95423bc6ae18457ccc359c8b6c0fa387.tar.bz2 | |
RISC-V: reduce redundancy in sign/zero extension macro insn handling
Fold M_{S,Z}EXTH, deriving signed-ness from the incoming mnemonic. Fold
riscv_ext()'s calls md_assemblef(), the first of which were entirely
identical, while the other pair differed in just a single character.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 39196e7..c9ba4c9 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1044,11 +1044,11 @@ const struct riscv_opcode riscv_opcodes[] = {"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, NULL, INSN_MACRO }, {"sext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_SEXT_H, MASK_C_SEXT_H, match_opcode, INSN_ALIAS }, {"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 }, -{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, NULL, INSN_MACRO }, +{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, INSN_MACRO }, {"zext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_ZEXT_H, MASK_C_ZEXT_H, match_opcode, INSN_ALIAS }, {"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 }, {"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 }, -{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, NULL, INSN_MACRO }, +{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, INSN_MACRO }, {"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 }, {"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 }, {"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 }, |