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| author | Alexandre Oliva <aoliva@redhat.com> | 2001-11-29 18:04:00 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@redhat.com> | 2001-11-29 18:04:00 +0000 |
| commit | e21c4a1c1b529bbce6c63e95ddb90b8d63ad0cde (patch) | |
| tree | a78c0fe24ca781c18d3c546aba916f4835fc342c /opcodes | |
| parent | 9b21d49b4ae70fcb24e5d5e57694dcf6b897b046 (diff) | |
| download | gdb-e21c4a1c1b529bbce6c63e95ddb90b8d63ad0cde.zip gdb-e21c4a1c1b529bbce6c63e95ddb90b8d63ad0cde.tar.gz gdb-e21c4a1c1b529bbce6c63e95ddb90b8d63ad0cde.tar.bz2 | |
* d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP.
(RSRC_SP): New macro.
(d10v_operands): Add it.
(d10v_opcodes): Adjust "st" and "st2w" to use RSRC_SP.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/d10v-opc.c | 12 |
2 files changed, 14 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ec8f120..ce35c88 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2001-11-29 Alexandre Oliva <aoliva@redhat.com> + + * d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP. + (RSRC_SP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Adjust "st" and "st2w" to use RSRC_SP. + 2001-11-23 Lars Brinkhoff <lars@nocrew.org> * pdp11-dis.c (print_insn_pdp11): Handle illegal instructions. diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c index 1e099b6..a4afa37 100644 --- a/opcodes/d10v-opc.c +++ b/opcodes/d10v-opc.c @@ -69,7 +69,7 @@ const struct pd_reg d10v_predefined_registers[] = { "r13", NULL, OPERAND_GPR+13 }, { "r14", NULL, OPERAND_GPR+14 }, { "r14-r15", NULL, OPERAND_GPR+14 }, - { "r15", "sp", OPERAND_GPR+15 }, + { "r15", "sp", OPERAND_SP|OPERAND_GPR+15 }, { "r2", NULL, OPERAND_GPR+2 }, { "r2-r3", NULL, OPERAND_GPR+2 }, { "r3", NULL, OPERAND_GPR+3 }, @@ -85,7 +85,7 @@ const struct pd_reg d10v_predefined_registers[] = { "rpt_c", NULL, OPERAND_CONTROL+7 }, { "rpt_e", NULL, OPERAND_CONTROL+9 }, { "rpt_s", NULL, OPERAND_CONTROL+8 }, - { "sp", NULL, OPERAND_GPR+15 }, + { "sp", NULL, OPERAND_SP|OPERAND_GPR+15 }, }; int @@ -100,7 +100,9 @@ const struct d10v_operand d10v_operands[] = { 0, 0, 0 }, #define RSRC (UNUSED + 1) { 4, 1, OPERAND_GPR|OPERAND_REG }, -#define RDST (RSRC + 1) +#define RSRC_SP (RSRC + 1) + { 4, 1, OPERAND_SP|OPERAND_GPR|OPERAND_REG }, +#define RDST (RSRC_SP + 1) { 4, 5, OPERAND_DEST|OPERAND_GPR|OPERAND_REG }, #define ASRC (RDST + 1) { 1, 4, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, @@ -311,13 +313,13 @@ const struct d10v_opcode d10v_opcodes[] = { { "srx", SHORT_2, 1, IU, PAR|RF0, 0x4609, 0x7e1f, { RDST } }, { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, - { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC_SP } }, { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } }, { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC, MINUS } }, { "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } }, { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } }, { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } }, - { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC_SP } }, { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } }, { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } }, { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } }, |