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authorJan Beulich <jbeulich@novell.com>2019-06-25 09:25:26 +0200
committerJan Beulich <jbeulich@suse.com>2019-06-25 09:35:17 +0200
commite1a1babdad9d14b935cbddc7d63fb76a580a16c5 (patch)
tree39fda81013c155f1b0e5dc365b2f9394147b951b /opcodes
parentb8364fa775112f036a80e799b70311f69baac131 (diff)
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x86: fix (dis)assembly of certain SSE2 insns in 16-bit mode
MOVNTI was wrongly assembled with a 66h prefix. Add IgnoreSize to address this. It and the scalar to/from integer conversion insns also were also wrongly using Ev / Gv, leading to 16-bit register names being printed when 32-bit ones were meant. Clone the 32-bit SSE2 test to cover both assembler and disassembler.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog8
-rw-r--r--opcodes/i386-dis.c14
-rw-r--r--opcodes/i386-opc.tbl2
-rw-r--r--opcodes/i386-tbl.h2
4 files changed, 17 insertions, 9 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c4c3e99..e02fd08 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,13 @@
2019-06-25 Jan Beulich <jbeulich@suse.com>
+ * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
+ Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
+ movnti.
+ * i386-opc.tbl (movnti): Add IgnoreSize.
+ * i386-tbl.h: Re-generate.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
* i386-opc.tbl (and): Mark Imm8S form for optimization.
* i386-tbl.h: Re-generate.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 1847855..f7d9641 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3728,9 +3728,9 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_0F2A */
{
{ "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
- { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
+ { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
{ "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
- { "cvtsi2sd%LQ", { XM, Ev }, 0 },
+ { "cvtsi2sd%LQ", { XM, Edq }, 0 },
},
/* PREFIX_0F2B */
@@ -3744,17 +3744,17 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_0F2C */
{
{ "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
{ "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2D */
{
{ "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
{ "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2E */
@@ -4063,7 +4063,7 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_MOD_0_0FC3 */
{
- { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
+ { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
},
/* PREFIX_MOD_0_0FC7_REG_6 */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b40fa8e..e6a3f61 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -945,7 +945,7 @@ fucompi, 1, 0xdfe8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
// Pentium4 extensions.
-movnti, 2, 0xfc3, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoAVX, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+movnti, 2, 0xfc3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoAVX, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
clflush, 1, 0xfae, 0x7, 2, CpuClflush, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex }
lfence, 0, 0xfae, 0xe8, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { 0 }
mfence, 0, 0xfae, 0xf0, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { 0 }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e0bd493..52b62d1 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -9736,7 +9736,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,