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authorJiong Wang <jiong.wang@arm.com>2014-09-03 14:45:26 +0100
committerJiong Wang <jiong.wang@arm.com>2014-09-03 14:53:53 +0100
commitdf7b4545b2b49572ab63690c130df973af109615 (patch)
tree49bdec91dcec920e99e5e3fd36fdc6c413d56e24 /opcodes
parentee804238f097e91088a340c15891170f2748b4fd (diff)
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[PATCH/AArch64] Generic support for all system registers using mrs and msr
2014-09-03 Jiong Wang <jiong.wang@arm.com> opcode/ * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr. * aarch64-dis-2.c: Update auto-generated file. gas/ * config/tc-aarch64.c (parse_sys_reg): Remove the restriction on op0 field. gas/testsuite/ * gas/aarch64/illegal.s: Update testcase. * gas/aarch64/illegal.d: Likewise. * gas/aarch64/sysreg-1.s: Likewise. * gas/aarch64/sysreg-1.d: Likewise.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/aarch64-dis-2.c120
-rw-r--r--opcodes/aarch64-tbl.h4
3 files changed, 28 insertions, 101 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a0b4e19..83118a5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2014-09-03 Jiong Wang <jiong.wang@arm.com>
+ * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
+ * aarch64-dis-2.c: Update auto-generated file.
+
+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
* aarch64-tbl.h (QL_R4NIL): New qualifiers.
(aarch64_feature_lse): New feature added.
(LSE): New Added.
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index a0f1a38..fd1da83 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -3250,109 +3250,21 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 21) & 0x1) == 0)
{
- if (((word >> 19) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
- {
- if (((word >> 13) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxx00xxxxx00xxx1x10x01x
- msr. */
- return 955;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxx01xxxxx00xxx1x10x01x
- hint. */
- return 956;
- }
- }
- else
- {
- if (((word >> 5) & 0x1) == 0)
- {
- if (((word >> 6) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxx00xxxxx1xxxxxx00xxx1x10x01x
- dsb. */
- return 964;
- }
- else
- {
- if (((word >> 7) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxx010xxxx1xxxxxx00xxx1x10x01x
- clrex. */
- return 963;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxx011xxxx1xxxxxx00xxx1x10x01x
- isb. */
- return 966;
- }
- }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxx1xxxxxx1xxxxxx00xxx1x10x01x
- dmb. */
- return 965;
- }
- }
- }
- else
- {
- if (((word >> 21) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxx100xx1x10x01x
- sys. */
- return 967;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxx101xx1x10x01x
- sysl. */
- return 973;
- }
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx1x10x01x
+ msr. */
+ return 955;
}
else
{
- if (((word >> 21) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxx10xx1x10x01x
- msr. */
- return 972;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxx11xx1x10x01x
- mrs. */
- return 974;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1xx1x10x01x
+ sysl. */
+ return 973;
}
}
}
@@ -8799,6 +8711,16 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
case 743: return NULL; /* stp --> NULL. */
case 740: value = 744; break; /* ldnp --> ldp. */
case 744: return NULL; /* ldp --> NULL. */
+ case 955: value = 956; break; /* msr --> hint. */
+ case 956: value = 963; break; /* hint --> clrex. */
+ case 963: value = 964; break; /* clrex --> dsb. */
+ case 964: value = 965; break; /* dsb --> dmb. */
+ case 965: value = 966; break; /* dmb --> isb. */
+ case 966: value = 967; break; /* isb --> sys. */
+ case 967: value = 972; break; /* sys --> msr. */
+ case 972: return NULL; /* msr --> NULL. */
+ case 973: value = 974; break; /* sysl --> mrs. */
+ case 974: return NULL; /* mrs --> NULL. */
case 355: value = 356; break; /* st4 --> st1. */
case 356: value = 357; break; /* st1 --> st2. */
case 357: value = 358; break; /* st2 --> st3. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 13a205f..1a16656 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2272,9 +2272,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"dc", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS},
{"ic", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
{"tlbi", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
- {"msr", 0xd5100000, 0xfff00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0},
+ {"msr", 0xd5000000, 0xffe00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0},
{"sysl", 0xd5280000, 0xfff80000, ic_system, 0, CORE, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0},
- {"mrs", 0xd5300000, 0xfff00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0},
+ {"mrs", 0xd5200000, 0xffe00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0},
/* Test & branch (immediate). */
{"tbz", 0x36000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
{"tbnz", 0x37000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},