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authorRichard Sandiford <rdsandiford@googlemail.com>2011-07-24 14:20:15 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2011-07-24 14:20:15 +0000
commitdf58fc944dbc6d5efd8d3826241b64b6af22f447 (patch)
treedb7e36d6606aec2a41f8226d6012dd4c38a2818e /opcodes
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2011-02-25 Chao-ying Fu <fu@mips.com> Ilie Garbacea <ilie@mips.com> Maciej W. Rozycki <macro@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * archures.c (bfd_mach_mips_micromips): New macro. * cpu-mips.c (I_micromips): New enum value. (arch_info_struct): Add bfd_mach_mips_micromips. * elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New prototype. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips16_elf_reloc_unshuffle): Rename to... (_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS ASE. (_bfd_mips16_elf_reloc_shuffle): Rename to... (_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE. (gprel16_reloc_p): Handle microMIPS ASE. (literal_reloc_p): New function. * elf32-mips.c (elf_micromips_howto_table_rel): New variable. (_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE. (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle and _bfd_mips_elf_reloc_shuffle changes. (mips_elf_gprel32_reloc): Update comment. (micromips_reloc_map): New variable. (bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE. (mips_elf32_rtype_to_howto): Likewise. (mips_info_to_howto_rel): Likewise. (bfd_elf32_bfd_is_target_special_symbol): Define. (bfd_elf32_bfd_relax_section): Likewise. * elf64-mips.c (micromips_elf64_howto_table_rel): New variable. (micromips_elf64_howto_table_rela): Likewise. (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle and _bfd_mips_elf_reloc_shuffle changes. (micromips_reloc_map): Likewise. (bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE. (bfd_elf64_bfd_reloc_name_lookup): Likewise. (mips_elf64_rtype_to_howto): Likewise. (bfd_elf64_bfd_is_target_special_symbol): Define. * elfn32-mips.c (elf_micromips_howto_table_rel): New variable. (elf_micromips_howto_table_rela): Likewise. (mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle and _bfd_mips_elf_reloc_shuffle changes. (micromips_reloc_map): Likewise. (bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE. (bfd_elf32_bfd_reloc_name_lookup): Likewise. (mips_elf_n32_rtype_to_howto): Likewise. (bfd_elf32_bfd_is_target_special_symbol): Define. * elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro. (LA25_LUI_MICROMIPS_2): Likewise. (LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise. (LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise. (TLS_RELOC_P): Handle microMIPS ASE. (mips_elf_create_stub_symbol): Adjust value of stub symbol if target is a microMIPS function. (micromips_reloc_p): New function. (micromips_reloc_shuffle_p): Likewise. (got16_reloc_p, call16_reloc_p): Handle microMIPS ASE. (got_disp_reloc_p, got_page_reloc_p): New functions. (got_ofst_reloc_p): Likewise. (got_hi16_reloc_p, got_lo16_reloc_p): Likewise. (call_hi16_reloc_p, call_lo16_reloc_p): Likewise. (hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE. (micromips_branch_reloc_p): New function. (tls_gd_reloc_p, tls_ldm_reloc_p): Likewise. (tls_gottprel_reloc_p): Likewise. (_bfd_mips16_elf_reloc_unshuffle): Rename to... (_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS ASE. (_bfd_mips16_elf_reloc_shuffle): Rename to... (_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE. (_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE. (mips_tls_got_index, mips_elf_got_page): Likewise. (mips_elf_create_local_got_entry): Likewise. (mips_elf_relocation_needs_la25_stub): Likewise. (mips_elf_calculate_relocation): Likewise. (mips_elf_perform_relocation): Likewise. (_bfd_mips_elf_symbol_processing): Likewise. (_bfd_mips_elf_add_symbol_hook): Likewise. (_bfd_mips_elf_link_output_symbol_hook): Likewise. (mips_elf_add_lo16_rel_addend): Likewise. (_bfd_mips_elf_check_relocs): Likewise. (mips_elf_adjust_addend): Likewise. (_bfd_mips_elf_relocate_section): Likewise. (mips_elf_create_la25_stub): Likewise. (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise. (_bfd_mips_elf_gc_sweep_hook): Likewise. (_bfd_mips_elf_is_target_special_symbol): New function. (mips_elf_relax_delete_bytes): Likewise. (opcode_descriptor): New structure. (RA): New macro. (OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise. (b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables. (beq_insn_32): Likewise. (b_insn_16, bz_insn_16): New variables. (BZC32_REG_FIELD): New macro. (bz_rs_insns_32, bz_rt_insns_32): New variables. (bzc_insns_32, bz_insns_16):Likewise. (BZ16_REG, BZ16_REG_FIELD): New macros. (jal_insn_32_bd16, jal_insn_32_bd32): New variables. (jal_x_insn_32_bd32): Likewise. (j_insn_32, jalr_insn_32): Likewise. (ds_insns_32_bd16, ds_insns_32_bd32): Likewise. (jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise. (JR16_REG): New macro. (ds_insns_16_bd16): New variable. (lui_insn): Likewise. (addiu_insn, addiupc_insn): Likewise. (ADDIUPC_REG_FIELD): New macro. (MOVE32_RD, MOVE32_RS): Likewise. (MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise. (move_insns_32, move_insns_16): New variables. (nop_insn_32, nop_insn_16): Likewise. (MATCH): New macro. (find_match): New function. (check_br16_dslot, check_br32_dslot): Likewise. (check_br16, check_br32): Likewise. (IS_BITSIZE): New macro. (check_4byte_branch): New function. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16 and microMIPS modules together. (_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE. * reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation. (BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise. (BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise. (BFD_RELOC_MICROMIPS_GPREL16): Likewise. (BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise. (BFD_RELOC_MICROMIPS_HI16_S): Likewise. (BFD_RELOC_MICROMIPS_LO16): Likewise. (BFD_RELOC_MICROMIPS_LITERAL): Likewise. (BFD_RELOC_MICROMIPS_GOT16): Likewise. (BFD_RELOC_MICROMIPS_CALL16): Likewise. (BFD_RELOC_MICROMIPS_GOT_HI16): Likewise. (BFD_RELOC_MICROMIPS_GOT_LO16): Likewise. (BFD_RELOC_MICROMIPS_CALL_HI16): Likewise. (BFD_RELOC_MICROMIPS_CALL_LO16): Likewise. (BFD_RELOC_MICROMIPS_SUB): Likewise. (BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise. (BFD_RELOC_MICROMIPS_GOT_OFST): Likewise. (BFD_RELOC_MICROMIPS_GOT_DISP): Likewise. (BFD_RELOC_MICROMIPS_HIGHEST): Likewise. (BFD_RELOC_MICROMIPS_HIGHER): Likewise. (BFD_RELOC_MICROMIPS_SCN_DISP): Likewise. (BFD_RELOC_MICROMIPS_JALR): Likewise. (BFD_RELOC_MICROMIPS_TLS_GD): Likewise. (BFD_RELOC_MICROMIPS_TLS_LDM): Likewise. (BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise. (BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise. (BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise. (BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise. (BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * readelf.c (get_machine_flags): Handle microMIPS ASE. (get_mips_symbol_other): Likewise. gas/ 2011-02-25 Maciej W. Rozycki <macro@codesourcery.com> Chao-ying Fu <fu@mips.com> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.h (mips_segment_info): Add one bit for microMIPS. (TC_LABEL_IS_LOCAL): New macro. (mips_label_is_local): New prototype. * config/tc-mips.c (S0, S7): New macros. (emit_branch_likely_macro): New variable. (mips_set_options): Add micromips. (mips_opts): Initialise micromips to -1. (file_ase_micromips): New variable. (CPU_HAS_MICROMIPS): New macro. (hilo_interlocks): Set for microMIPS too. (gpr_interlocks): Likewise. (cop_interlocks): Likewise. (cop_mem_interlocks): Likewise. (HAVE_CODE_COMPRESSION): New macro. (micromips_op_hash): New variable. (micromips_nop16_insn, micromips_nop32_insn): New variables. (NOP_INSN): Handle microMIPS ASE. (mips32_to_micromips_reg_b_map): New macro. (mips32_to_micromips_reg_c_map): Likewise. (mips32_to_micromips_reg_d_map): Likewise. (mips32_to_micromips_reg_e_map): Likewise. (mips32_to_micromips_reg_f_map): Likewise. (mips32_to_micromips_reg_g_map): Likewise. (mips32_to_micromips_reg_l_map): Likewise. (mips32_to_micromips_reg_n_map): Likewise. (mips32_to_micromips_reg_h_map): New variable. (mips32_to_micromips_reg_m_map): Likewise. (mips32_to_micromips_reg_q_map): Likewise. (micromips_to_32_reg_h_map): New variable. (micromips_to_32_reg_i_map): Likewise. (micromips_to_32_reg_m_map): Likewise. (micromips_to_32_reg_q_map): Likewise. (micromips_to_32_reg_b_map): New macro. (micromips_to_32_reg_c_map): Likewise. (micromips_to_32_reg_d_map): Likewise. (micromips_to_32_reg_e_map): Likewise. (micromips_to_32_reg_f_map): Likewise. (micromips_to_32_reg_g_map): Likewise. (micromips_to_32_reg_l_map): Likewise. (micromips_to_32_reg_n_map): Likewise. (micromips_imm_b_map, micromips_imm_c_map): New macros. (RELAX_DELAY_SLOT_16BIT): New macro. (RELAX_DELAY_SLOT_SIZE_FIRST): Likewise. (RELAX_DELAY_SLOT_SIZE_SECOND): Likewise. (RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros. (RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise. (RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise. (RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise. (RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise. (RELAX_MICROMIPS_MARK_TOOFAR16): Likewise. (RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise. (RELAX_MICROMIPS_TOOFAR32): Likewise. (RELAX_MICROMIPS_MARK_TOOFAR32): Likewise. (RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise. (INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE. (mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p, fsize and insns. (mips_mark_labels): New function. (mips16_small, mips16_ext): Remove variables, replacing with... (forced_insn_size): ... this. (append_insn, mips16_ip): Update accordingly. (micromips_insn_length): New function. (insn_length): Return the length of microMIPS instructions. (mips_record_mips16_mode): Rename to... (mips_record_compressed_mode): ... this. Handle microMIPS ASE. (install_insn): Handle microMIPS ASE. (reglist_lookup): New function. (is_size_valid, is_delay_slot_valid): Likewise. (md_begin): Handle microMIPS ASE. (md_assemble): Likewise. Update for append_insn interface change. (micromips_reloc_p): New function. (got16_reloc_p): Handle microMIPS ASE. (hi16_reloc_p): Likewise. (lo16_reloc_p): Likewise. (jmp_reloc_p): New function. (jalr_reloc_p): Likewise. (matching_lo_reloc): Handle microMIPS ASE. (insn_uses_reg, reg_needs_delay): Likewise. (mips_move_labels): Likewise. (mips16_mark_labels): Rename to... (mips_compressed_mark_labels): ... this. Handle microMIPS ASE. (gpr_mod_mask): New function. (gpr_read_mask, gpr_write_mask): Handle microMIPS ASE. (fpr_read_mask, fpr_write_mask): Likewise. (insns_between, nops_for_vr4130, nops_for_insn): Likewise. (fix_loongson2f_nop, fix_loongson2f_jump): Likewise. (MICROMIPS_LABEL_CHAR): New macro. (micromips_target_label, micromips_target_name): New variables. (micromips_label_name, micromips_label_expr): New functions. (micromips_label_inc, micromips_add_label): Likewise. (mips_label_is_local): Likewise. (micromips_map_reloc): Likewise. (can_swap_branch_p): Handle microMIPS ASE. (append_insn): Add expansionp argument. Handle microMIPS ASE. (start_noreorder, end_noreorder): Handle microMIPS ASE. (macro_start, macro_warning, macro_end): Likewise. (brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables. (mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise. (BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros. (MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise. (macro_build): Handle microMIPS ASE. Update for append_insn interface change. (mips16_macro_build): Update for append_insn interface change. (macro_build_jalr): Handle microMIPS ASE. (macro_build_lui): Likewise. Simplify. (load_register): Handle microMIPS ASE. (load_address): Likewise. (move_register): Likewise. (macro_build_branch_likely): New function. (macro_build_branch_ccl): Likewise. (macro_build_branch_rs): Likewise. (macro_build_branch_rsrt): Likewise. (macro): Handle microMIPS ASE. (validate_micromips_insn): New function. (expr_const_in_range): Likewise. (mips_ip): Handle microMIPS ASE. (options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS. (md_longopts): Add mmicromips and mno-micromips. (md_parse_option): Handle OPTION_MICROMIPS and OPTION_NO_MICROMIPS. (mips_after_parse_args): Handle microMIPS ASE. (md_pcrel_from): Handle microMIPS relocations. (mips_force_relocation): Likewise. (md_apply_fix): Likewise. (mips_align): Handle microMIPS ASE. (s_mipsset): Likewise. (s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers. (s_dtprel_internal): Likewise. (s_gpword, s_gpdword): Likewise. (s_insn): Handle microMIPS ASE. (s_mips_stab): Likewise. (relaxed_micromips_32bit_branch_length): New function. (relaxed_micromips_16bit_branch_length): New function. (md_estimate_size_before_relax): Handle microMIPS ASE. (mips_fix_adjustable): Likewise. (tc_gen_reloc): Handle microMIPS relocations. (mips_relax_frag): Handle microMIPS ASE. (md_convert_frag): Likewise. (mips_frob_file_after_relocs): Likewise. (mips_elf_final_processing): Likewise. (mips_nop_opcode): Likewise. (mips_handle_align): Likewise. (md_show_usage): Handle microMIPS options. * symbols.c (TC_LABEL_IS_LOCAL): New macro. (S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check. * doc/as.texinfo (Target MIPS options): Add -mmicromips and -mno-micromips. (-mmicromips, -mno-micromips): New options. * doc/c-mips.texi (-mmicromips, -mno-micromips): New options. (MIPS ISA): Document .set micromips and .set nomicromips. (MIPS insn): Update for microMIPS support. gas/testsuite/ 2011-02-25 Maciej W. Rozycki <macro@codesourcery.com> Chao-ying Fu <fu@mips.com> Richard Sandiford <rdsandiford@googlemail.com> * gas/mips/micromips.d: New test. * gas/mips/micromips-branch-delay.d: Likewise. * gas/mips/micromips-branch-relax.d: Likewise. * gas/mips/micromips-branch-relax-pic.d: Likewise. * gas/mips/micromips-size-1.d: Likewise. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips.l: New stderr output. * gas/mips/micromips-branch-delay.l: Likewise. * gas/mips/micromips-branch-relax.l: Likewise. * gas/mips/micromips-branch-relax-pic.l: Likewise. * gas/mips/micromips-size-0.l: New list test. * gas/mips/micromips-size-1.l: New stderr output. * gas/mips/micromips.s: New test source. * gas/mips/micromips-branch-delay.s: Likewise. * gas/mips/micromips-branch-relax.s: Likewise. * gas/mips/micromips-size-0.s: Likewise. * gas/mips/micromips-size-1.s: Likewise. * gas/mips/mips.exp: Run the new tests. * gas/mips/dli.s: Use .p2align. * gas/mips/elf_ase_micromips.d: New test. * gas/mips/elf_ase_micromips-2.d: Likewise. * gas/mips/micromips@abs.d: Likewise. * gas/mips/micromips@add.d: Likewise. * gas/mips/micromips@alnv_ps-swap.d: Likewise. * gas/mips/micromips@and.d: Likewise. * gas/mips/micromips@beq.d: Likewise. * gas/mips/micromips@bge.d: Likewise. * gas/mips/micromips@bgeu.d: Likewise. * gas/mips/micromips@blt.d: Likewise. * gas/mips/micromips@bltu.d: Likewise. * gas/mips/micromips@branch-likely.d: Likewise. * gas/mips/micromips@branch-misc-1.d: Likewise. * gas/mips/micromips@branch-misc-2-64.d: Likewise. * gas/mips/micromips@branch-misc-2.d: Likewise. * gas/mips/micromips@branch-misc-2pic-64.d: Likewise. * gas/mips/micromips@branch-misc-2pic.d: Likewise. * gas/mips/micromips@branch-misc-4-64.d: Likewise. * gas/mips/micromips@branch-misc-4.d: Likewise. * gas/mips/micromips@branch-self.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@daddi.d: Likewise. * gas/mips/micromips@dli.d: Likewise. * gas/mips/micromips@elf-jal.d: Likewise. * gas/mips/micromips@elf-rel2.d: Likewise. * gas/mips/micromips@elfel-rel2.d: Likewise. * gas/mips/micromips@elf-rel4.d: Likewise. * gas/mips/micromips@jal-svr4pic.d: Likewise. * gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise. * gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise. * gas/mips/micromips@li.d: Likewise. * gas/mips/micromips@loc-swap-dis.d: Likewise. * gas/mips/micromips@loc-swap.d: Likewise. * gas/mips/micromips@mips1-fp.d: Likewise. * gas/mips/micromips@mips32-cp2.d: Likewise. * gas/mips/micromips@mips32-imm.d: Likewise. * gas/mips/micromips@mips32-sf32.d: Likewise. * gas/mips/micromips@mips32.d: Likewise. * gas/mips/micromips@mips32r2-cp2.d: Likewise. * gas/mips/micromips@mips32r2-fp32.d: Likewise. * gas/mips/micromips@mips32r2-sync.d: Likewise. * gas/mips/micromips@mips32r2.d: Likewise. * gas/mips/micromips@mips4-branch-likely.d: Likewise. * gas/mips/micromips@mips4-fp.d: Likewise. * gas/mips/micromips@mips4.d: Likewise. * gas/mips/micromips@mips5.d: Likewise. * gas/mips/micromips@mips64-cp2.d: Likewise. * gas/mips/micromips@mips64.d: Likewise. * gas/mips/micromips@mips64r2.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips@relax-at.d: Likewise. * gas/mips/micromips@relax.d: Likewise. * gas/mips/micromips@rol-hw.d: Likewise. * gas/mips/micromips@uld2-eb.d: Likewise. * gas/mips/micromips@uld2-el.d: Likewise. * gas/mips/micromips@ulh2-eb.d: Likewise. * gas/mips/micromips@ulh2-el.d: Likewise. * gas/mips/micromips@ulw2-eb-ilocks.d: Likewise. * gas/mips/micromips@ulw2-el-ilocks.d: Likewise. * gas/mips/cache.d: Likewise. * gas/mips/daddi.d: Likewise. * gas/mips/mips32-imm.d: Likewise. * gas/mips/pref.d: Likewise. * gas/mips/elf-rel27.d: Handle microMIPS ASE. * gas/mips/l_d.d: Likewise. * gas/mips/l_d-n32.d: Likewise. * gas/mips/l_d-n64.d: Likewise. * gas/mips/ld.d: Likewise. * gas/mips/ld-n32.d: Likewise. * gas/mips/ld-n64.d: Likewise. * gas/mips/s_d.d: Likewise. * gas/mips/s_d-n32.d: Likewise. * gas/mips/s_d-n64.d: Likewise. * gas/mips/sd.d: Likewise. * gas/mips/sd-n32.d: Likewise. * gas/mips/sd-n64.d: Likewise. * gas/mips/mips32.d: Update immediates. * gas/mips/micromips@mips32-cp2.s: New test source. * gas/mips/micromips@mips32-imm.s: Likewise. * gas/mips/micromips@mips32r2-cp2.s: Likewise. * gas/mips/micromips@mips64-cp2.s: Likewise. * gas/mips/cache.s: Likewise. * gas/mips/daddi.s: Likewise. * gas/mips/mips32-imm.s: Likewise. * gas/mips/elf-rel4.s: Handle microMIPS ASE. * gas/mips/lb-pic.s: Likewise. * gas/mips/ld.s: Likewise. * gas/mips/mips32.s: Likewise. * gas/mips/mips.exp: Add the micromips arch. Exclude mips16e from micromips. Run mips32-imm. * gas/mips/jal-mask-11.d: New test. * gas/mips/jal-mask-12.d: Likewise. * gas/mips/micromips@jal-mask-11.d: Likewise. * gas/mips/jal-mask-1.s: Source for the new tests. * gas/mips/jal-mask-21.d: New test. * gas/mips/jal-mask-22.d: Likewise. * gas/mips/micromips@jal-mask-12.d: Likewise. * gas/mips/jal-mask-2.s: Source for the new tests. * gas/mips/mips.exp: Run the new tests. * gas/mips/mips16-e.d: Add --special-syms to `objdump'. * gas/mips/tmips16-e.d: Likewise. * gas/mips/mipsel16-e.d: Likewise. * gas/mips/tmipsel16-e.d: Likewise. * gas/mips/and.s: Adjust padding. * gas/mips/beq.s: Likewise. * gas/mips/bge.s: Likewise. * gas/mips/bgeu.s: Likewise. * gas/mips/blt.s: Likewise. * gas/mips/bltu.s: Likewise. * gas/mips/branch-misc-2.s: Likewise. * gas/mips/jal.s: Likewise. * gas/mips/li.s: Likewise. * gas/mips/mips4.s: Likewise. * gas/mips/mips4-fp.s: Likewise. * gas/mips/relax.s: Likewise. * gas/mips/and.d: Update accordingly. * gas/mips/elf-jal.d: Likewise. * gas/mips/jal.d: Likewise. * gas/mips/li.d: Likewise. * gas/mips/relax-at.d: Likewise. * gas/mips/relax.d: Likewise. include/elf/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * mips.h (R_MICROMIPS_min): New relocations. (R_MICROMIPS_26_S1): Likewise. (R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise. (R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise. (R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise. (R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise. (R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise. (R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise. (R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise. (R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise. (R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise. (R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise. (R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise. (R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise. (R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise. (R_MICROMIPS_TLS_GOTTPREL): Likewise. (R_MICROMIPS_TLS_TPREL_HI16): Likewise. (R_MICROMIPS_TLS_TPREL_LO16): Likewise. (R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise. (R_MICROMIPS_max): Likewise. (EF_MIPS_ARCH_ASE_MICROMIPS): New macro. (STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise. (ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise. (STO_MICROMIPS): Likewise. (ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise. (ELF_ST_IS_COMPRESSED): Likewise. (STO_MIPS_PLT, STO_MIPS_PIC): Rework. (ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise. (STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise. include/opcode/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. (OP_MASK_STYPE, OP_SH_STYPE): Likewise. (OP_MASK_CODE10, OP_SH_CODE10): Likewise. (OP_MASK_TRAP, OP_SH_TRAP): Likewise. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise. (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise. (OP_MASK_RS3, OP_SH_RS3): Likewise. (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise. (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise. (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise. (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise. (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise. (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise. (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise. (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise. (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise. (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise. (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise. (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise. (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise. (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise. (INSN_WRITE_GPR_S): New macro. (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise. (INSN2_READ_FPR_D): Likewise. (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise. (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise. (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise. (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise. (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise. (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise. (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise. (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise. (CPU_MICROMIPS): New macro. (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values. (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise. (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise. (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise. (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise. (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise. (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise. (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise. (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise. (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise. (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise. (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise. (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise. (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros. (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise. (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise. (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise. (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise. (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise. (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise. (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise. (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise. (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise. (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise. (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise. (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise. (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise. (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise. (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise. (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise. (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise. (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise. (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise. (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise. (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise. (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise. (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise. (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise. (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise. (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise. (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise. (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise. (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise. (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise. (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise. (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise. (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise. (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise. (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise. (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise. (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise. (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise. (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise. (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise. (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise. (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise. (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise. (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise. (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise. (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise. (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise. (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise. (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise. (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise. (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise. (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise. (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise. (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise. (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise. (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise. (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise. (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise. (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise. (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise. (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise. (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise. (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise. (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise. (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise. (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise. (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise. (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise. (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise. (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise. (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise. (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise. (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise. (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise. (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise. (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise. (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise. (micromips_opcodes): New declaration. (bfd_micromips_num_opcodes): Likewise. ld/testsuite/ 2011-02-25 Catherine Moore <clm@codesourcery.com> Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * lib/ld-lib.exp (run_dump_test): Support distinct assembler flags for the same source named multiple times. * ld-mips-elf/jalx-1.s: New test source. * ld-mips-elf/jalx-1.d: New test output. * ld-mips-elf/jalx-1.ld: New test linker script. * ld-mips-elf/jalx-2-main.s: New test source. * ld-mips-elf/jalx-2-ex.s: Likewise. * ld-mips-elf/jalx-2-printf.s: Likewise. * ld-mips-elf/jalx-2.dd: New test output. * ld-mips-elf/jalx-2.ld: New test linker script. * ld-mips-elf/mips16-and-micromips.d: New test. * ld-mips-elf/mips-elf.exp: Run the new tests opcodes/ 2011-02-25 Chao-ying Fu <fu@mips.com> Maciej W. Rozycki <macro@codesourcery.com> * micromips-opc.c: New file. * mips-dis.c (micromips_to_32_reg_b_map): New array. (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise. (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise. (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise. (micromips_to_32_reg_q_map): Likewise. (micromips_imm_b_map, micromips_imm_c_map): Likewise. (micromips_ase): New variable. (is_micromips): New function. (set_default_mips_dis_options): Handle microMIPS ASE. (print_insn_micromips): New function. (is_compressed_mode_p): Likewise. (_print_insn_mips): Handle microMIPS instructions. * Makefile.am (CFILES): Add micromips-opc.c. * configure.in (bfd_mips_arch): Add micromips-opc.lo. * Makefile.in: Regenerate. * configure: Regenerate. * mips-dis.c (micromips_to_32_reg_h_map): New variable. (micromips_to_32_reg_i_map): Likewise. (micromips_to_32_reg_m_map): Likewise. (micromips_to_32_reg_n_map): New macro.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog26
-rw-r--r--opcodes/Makefile.am1
-rw-r--r--opcodes/Makefile.in1
-rwxr-xr-xopcodes/configure2
-rw-r--r--opcodes/configure.in2
-rw-r--r--opcodes/micromips-opc.c956
-rw-r--r--opcodes/mips-dis.c847
7 files changed, 1821 insertions, 14 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 642490c..9b5494e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,29 @@
+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c: New file.
+ * mips-dis.c (micromips_to_32_reg_b_map): New array.
+ (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
+ (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
+ (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
+ (micromips_to_32_reg_q_map): Likewise.
+ (micromips_imm_b_map, micromips_imm_c_map): Likewise.
+ (micromips_ase): New variable.
+ (is_micromips): New function.
+ (set_default_mips_dis_options): Handle microMIPS ASE.
+ (print_insn_micromips): New function.
+ (is_compressed_mode_p): Likewise.
+ (_print_insn_mips): Handle microMIPS instructions.
+ * Makefile.am (CFILES): Add micromips-opc.c.
+ * configure.in (bfd_mips_arch): Add micromips-opc.lo.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+
+ * mips-dis.c (micromips_to_32_reg_h_map): New variable.
+ (micromips_to_32_reg_i_map): Likewise.
+ (micromips_to_32_reg_m_map): Likewise.
+ (micromips_to_32_reg_n_map): New macro.
+
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips-opc.c (NODS): New macro.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 26f7580..2fd2cd5 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -159,6 +159,7 @@ TARGET_LIBOPCODES_CFILES = \
mep-ibld.c \
mep-opc.c \
microblaze-dis.c \
+ micromips-opc.c \
mips-dis.c \
mips-opc.c \
mips16-opc.c \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 7b27955..82fadb27 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -429,6 +429,7 @@ TARGET_LIBOPCODES_CFILES = \
mep-ibld.c \
mep-opc.c \
microblaze-dis.c \
+ micromips-opc.c \
mips-dis.c \
mips-opc.c \
mips16-opc.c \
diff --git a/opcodes/configure b/opcodes/configure
index 47f9393..746070e 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12440,7 +12440,7 @@ if test x${all_targets} = xfalse ; then
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;;
- bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
+ bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo micromips-opc.lo" ;;
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 0e35a18..3776be3 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -254,7 +254,7 @@ if test x${all_targets} = xfalse ; then
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;;
- bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
+ bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo micromips-opc.lo" ;;
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;;
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
new file mode 100644
index 0000000..0a312c1
--- /dev/null
+++ b/opcodes/micromips-opc.c
@@ -0,0 +1,956 @@
+/* micromips-opc.c. microMIPS opcode table.
+ Copyright 2008 Free Software Foundation, Inc.
+ Contributed by Chao-ying Fu, MIPS Technologies, Inc.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include <stdio.h>
+#include "sysdep.h"
+#include "opcode/mips.h"
+
+#define UBD INSN_UNCOND_BRANCH_DELAY
+#define CBD INSN_COND_BRANCH_DELAY
+#define TRAP INSN_TRAP
+#define SM INSN_STORE_MEMORY
+#define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */
+#define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */
+
+/* For 16-bit/32-bit microMIPS instructions. They are used in pinfo2. */
+#define UBR INSN2_UNCOND_BRANCH
+#define CBR INSN2_COND_BRANCH
+#define MOD_mb INSN2_MOD_GPR_MB
+#define MOD_mc INSN2_MOD_GPR_MC
+#define MOD_md INSN2_MOD_GPR_MD
+#define MOD_me INSN2_MOD_GPR_ME
+#define MOD_mf INSN2_MOD_GPR_MF
+#define MOD_mg INSN2_MOD_GPR_MG
+#define MOD_mhi INSN2_MOD_GPR_MHI
+#define MOD_mj INSN2_MOD_GPR_MJ
+#define MOD_ml MOD_mc /* Reuse, since the bit position is the same. */
+#define MOD_mm INSN2_MOD_GPR_MM
+#define MOD_mn INSN2_MOD_GPR_MN
+#define MOD_mp INSN2_MOD_GPR_MP
+#define MOD_mq INSN2_MOD_GPR_MQ
+#define MOD_sp INSN2_MOD_SP
+#define RD_31 INSN2_READ_GPR_31
+#define RD_gp INSN2_READ_GP
+#define RD_pc INSN2_READ_PC
+
+/* For 32-bit microMIPS instructions. */
+#define WR_s INSN2_WRITE_GPR_S /* Used in pinfo2. */
+#define WR_d INSN_WRITE_GPR_D
+#define WR_t INSN_WRITE_GPR_T
+#define WR_31 INSN_WRITE_GPR_31
+#define WR_D INSN_WRITE_FPR_D
+#define WR_T INSN_WRITE_FPR_T
+#define WR_S INSN_WRITE_FPR_S
+#define WR_CC INSN_WRITE_COND_CODE
+
+#define RD_s INSN_READ_GPR_S
+#define RD_b INSN_READ_GPR_S
+#define RD_t INSN_READ_GPR_T
+#define RD_T INSN_READ_FPR_T
+#define RD_S INSN_READ_FPR_S
+#define RD_R INSN_READ_FPR_R
+#define RD_D INSN2_READ_FPR_D /* Used in pinfo2. */
+#define RD_CC INSN_READ_COND_CODE
+#define RD_C0 INSN_COP
+#define RD_C1 INSN_COP
+#define RD_C2 INSN_COP
+#define WR_C0 INSN_COP
+#define WR_C1 INSN_COP
+#define WR_C2 INSN_COP
+#define CP INSN_COP
+
+#define WR_HI INSN_WRITE_HI
+#define RD_HI INSN_READ_HI
+
+#define WR_LO INSN_WRITE_LO
+#define RD_LO INSN_READ_LO
+
+#define WR_HILO WR_HI|WR_LO
+#define RD_HILO RD_HI|RD_LO
+#define MOD_HILO WR_HILO|RD_HILO
+
+/* Reuse INSN_ISA1 for 32-bit microMIPS ISA. All instructions in I1
+ are accepted as 32-bit microMIPS ISA.
+ Reuse INSN_ISA3 for 64-bit microMIPS ISA. All instructions in I3
+ are accepted as 64-bit microMIPS ISA. */
+#define I1 INSN_ISA1
+#define I3 INSN_ISA3
+
+const struct mips_opcode micromips_opcodes[] =
+{
+/* These instructions appear first so that the disassembler will find
+ them first. The assemblers uses a hash table based on the
+ instruction name anyhow. */
+/* name, args, match, mask, pinfo, pinfo2, membership */
+{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
+{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
+{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
+{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I1 },
+{"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1 },
+{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"ehb", "", 0x00001800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"pause", "", 0x00002800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"li", "md,mI", 0xec00, 0xfc00, 0, MOD_md, I1 },
+{"li", "t,j", 0x30000000, 0xfc1f0000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
+{"li", "t,i", 0x50000000, 0xfc1f0000, WR_t, INSN2_ALIAS, I1 }, /* ori */
+#if 0
+/* Disabled until we can handle 48-bit opcodes. */
+{"li", "s,I", 0x7c0000010000, 0xfc00001f0000, WR_t, 0, I3 }, /* li48 */
+#endif
+{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
+{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
+{"move", "mp,mj", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 },
+{"move", "d,s", 0x58000150, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I3 }, /* daddu */
+{"move", "d,s", 0x00000150, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I1 }, /* addu */
+{"move", "d,s", 0x00000290, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I1 }, /* or */
+{"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1 },
+{"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1 }, /* beq 0, 0 */
+{"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1 }, /* bgez 0 */
+{"bal", "p", 0x40600000, 0xffff0000, UBD|WR_31, INSN2_ALIAS|BD32, I1 }, /* bgezal 0 */
+{"bals", "p", 0x42600000, 0xffff0000, UBD|WR_31, INSN2_ALIAS|BD16, I1 }, /* bgezals 0 */
+{"bc", "p", 0x40e00000, 0xffff0000, TRAP, INSN2_ALIAS|UBR, I1 }, /* beqzc 0 */
+
+{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
+{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
+{"add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"add.s", "D,V,T", 0x54000030, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"add.ps", "D,V,T", 0x54000230, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"addi", "t,r,j", 0x10000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"addiu", "mp,mj,mZ", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"addiu", "md,ms,mW", 0x6c01, 0xfc01, 0, MOD_md|MOD_sp, I1 }, /* addiur1sp */
+{"addiu", "md,mc,mB", 0x6c00, 0xfc01, 0, MOD_md|MOD_mc, I1 }, /* addiur2 */
+{"addiu", "ms,mt,mY", 0x4c01, 0xfc01, 0, MOD_sp, I1 }, /* addiusp */
+{"addiu", "mp,mt,mX", 0x4c00, 0xfc01, 0, MOD_mp, I1 }, /* addius5 */
+{"addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, 0, MOD_mb|RD_pc, I1 }, /* addiupc */
+{"addiu", "t,r,j", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"addiupc", "mb,mQ", 0x78000000, 0xfc000000, 0, MOD_mb|RD_pc, I1 },
+{"addiur1sp", "md,mW", 0x6c01, 0xfc01, 0, MOD_md|MOD_sp, I1 },
+{"addiur2", "md,mc,mB", 0x6c00, 0xfc01, 0, MOD_md|MOD_mc, I1 },
+{"addiusp", "mY", 0x4c01, 0xfc01, 0, MOD_sp, I1 },
+{"addius5", "mp,mX", 0x4c00, 0xfc01, 0, MOD_mp, I1 },
+{"addu", "mp,mj,mz", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"addu", "mp,mz,mj", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"addu", "md,me,ml", 0x0400, 0xfc01, 0, MOD_md|MOD_me|MOD_ml, I1 },
+{"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
+/* We have no flag to mark the read from "y", so we use TRAP to disable
+ delay slot scheduling of ALNV.PS altogether. */
+{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, TRAP|WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"and", "mf,mt,mg", 0x4480, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"and", "mf,mg,mx", 0x4480, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
+{"andi", "md,mc,mC", 0x2c00, 0xfc00, 0, MOD_md|MOD_mc, I1 },
+{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+/* b is at the top of the table. */
+/* bal is at the top of the table. */
+{"bc1f", "p", 0x43800000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1f", "N,p", 0x43800000, 0xffe30000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1fl", "p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc1fl", "N,p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc2f", "p", 0x42800000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc2f", "N,p", 0x42800000, 0xffe30000, CBD|RD_CC, 0, I1 },
+{"bc2fl", "p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1 },
+{"bc2fl", "N,p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1 },
+{"bc1t", "p", 0x43a00000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1t", "N,p", 0x43a00000, 0xffe30000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1tl", "p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc1tl", "N,p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc2t", "p", 0x42a00000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc2t", "N,p", 0x42a00000, 0xffe30000, CBD|RD_CC, 0, I1 },
+{"bc2tl", "p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1 },
+{"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1 },
+{"beqz", "md,mE", 0x8c00, 0xfc00, CBD, MOD_md, I1 },
+{"beqz", "s,p", 0x94000000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"beqzc", "s,p", 0x40e00000, 0xffe00000, TRAP|RD_s, CBR, I1 },
+{"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1 },
+{"beq", "md,mz,mE", 0x8c00, 0xfc00, CBD, MOD_md, I1 }, /* beqz */
+{"beq", "mz,md,mE", 0x8c00, 0xfc00, CBD, MOD_md, I1 }, /* beqz */
+{"beq", "s,t,p", 0x94000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
+{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
+{"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1 },
+{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1 },
+{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
+{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
+{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I1 },
+{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I1 },
+{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
+{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
+{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I1 },
+{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I1 },
+{"bgez", "s,p", 0x40400000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bgezl", "s,p", 0, (int) M_BGEZL, INSN_MACRO, 0, I1 },
+{"bgezal", "s,p", 0x40600000, 0xffe00000, CBD|RD_s|WR_31, BD32, I1 },
+{"bgezals", "s,p", 0x42600000, 0xffe00000, CBD|RD_s|WR_31, BD16, I1 },
+{"bgezall", "s,p", 0, (int) M_BGEZALL, INSN_MACRO, 0, I1 },
+{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
+{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
+{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I1 },
+{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I1 },
+{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
+{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
+{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I1 },
+{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I1 },
+{"bgtz", "s,p", 0x40c00000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bgtzl", "s,p", 0, (int) M_BGTZL, INSN_MACRO, 0, I1 },
+{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
+{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
+{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I1 },
+{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I1 },
+{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
+{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
+{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I1 },
+{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I1 },
+{"blez", "s,p", 0x40800000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"blezl", "s,p", 0, (int) M_BLEZL, INSN_MACRO, 0, I1 },
+{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
+{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
+{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I1 },
+{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I1 },
+{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
+{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
+{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I1 },
+{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I1 },
+{"bltz", "s,p", 0x40000000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bltzl", "s,p", 0, (int) M_BLTZL, INSN_MACRO, 0, I1 },
+{"bltzal", "s,p", 0x40200000, 0xffe00000, CBD|RD_s|WR_31, BD32, I1 },
+{"bltzals", "s,p", 0x42200000, 0xffe00000, CBD|RD_s|WR_31, BD16, I1 },
+{"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1 },
+{"bnez", "md,mE", 0xac00, 0xfc00, CBD, MOD_md, I1 },
+{"bnez", "s,p", 0xb4000000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bnezc", "s,p", 0x40a00000, 0xffe00000, TRAP|RD_s, CBR, I1 },
+{"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1 },
+{"bne", "md,mz,mE", 0xac00, 0xfc00, CBD, MOD_md, I1 }, /* bnez */
+{"bne", "mz,md,mE", 0xac00, 0xfc00, CBD, MOD_md, I1 }, /* bnez */
+{"bne", "s,t,p", 0xb4000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
+{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
+{"bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1 },
+{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1 },
+{"break", "", 0x4680, 0xffff, TRAP, 0, I1 },
+{"break", "", 0x00000007, 0xffffffff, TRAP, 0, I1 },
+{"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1 },
+{"break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1 },
+{"break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1 },
+{"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.un.s", "M,S,T", 0x5400007c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.un.ps", "S,T", 0x5400087c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.un.ps", "M,S,T", 0x5400087c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.eq.d", "S,T", 0x540004bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.eq.d", "M,S,T", 0x540004bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.eq.s", "S,T", 0x540000bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.eq.s", "M,S,T", 0x540000bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.eq.ps", "S,T", 0x540008bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.eq.ps", "M,S,T", 0x540008bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ueq.d", "S,T", 0x540004fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ueq.d", "M,S,T", 0x540004fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ueq.s", "S,T", 0x540000fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ueq.s", "M,S,T", 0x540000fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ueq.ps", "S,T", 0x540008fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ueq.ps", "M,S,T", 0x540008fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.olt.d", "S,T", 0x5400053c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.olt.d", "M,S,T", 0x5400053c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.olt.s", "S,T", 0x5400013c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.olt.s", "M,S,T", 0x5400013c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.olt.ps", "S,T", 0x5400093c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.olt.ps", "M,S,T", 0x5400093c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ult.d", "S,T", 0x5400057c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ult.d", "M,S,T", 0x5400057c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ult.s", "S,T", 0x5400017c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ult.s", "M,S,T", 0x5400017c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ult.ps", "S,T", 0x5400097c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ult.ps", "M,S,T", 0x5400097c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ole.d", "S,T", 0x540005bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ole.d", "M,S,T", 0x540005bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ole.s", "S,T", 0x540001bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ole.s", "M,S,T", 0x540001bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ole.ps", "S,T", 0x540009bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ole.ps", "M,S,T", 0x540009bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ule.d", "S,T", 0x540005fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ule.d", "M,S,T", 0x540005fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ule.s", "S,T", 0x540001fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ule.s", "M,S,T", 0x540001fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ule.ps", "S,T", 0x540009fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ule.ps", "M,S,T", 0x540009fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.sf.d", "S,T", 0x5400063c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.sf.d", "M,S,T", 0x5400063c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.sf.s", "S,T", 0x5400023c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.sf.s", "M,S,T", 0x5400023c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.sf.ps", "S,T", 0x54000a3c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.sf.ps", "M,S,T", 0x54000a3c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngle.d", "S,T", 0x5400067c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngle.d", "M,S,T", 0x5400067c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngle.s", "S,T", 0x5400027c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngle.s", "M,S,T", 0x5400027c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngle.ps", "S,T", 0x54000a7c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngle.ps", "M,S,T", 0x54000a7c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.seq.d", "S,T", 0x540006bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.seq.d", "M,S,T", 0x540006bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.seq.s", "S,T", 0x540002bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.seq.s", "M,S,T", 0x540002bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.seq.ps", "S,T", 0x54000abc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.seq.ps", "M,S,T", 0x54000abc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngl.d", "S,T", 0x540006fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngl.d", "M,S,T", 0x540006fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngl.s", "S,T", 0x540002fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngl.s", "M,S,T", 0x540002fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngl.ps", "S,T", 0x54000afc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngl.ps", "M,S,T", 0x54000afc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.lt.d", "S,T", 0x5400073c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.lt.d", "M,S,T", 0x5400073c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.lt.s", "S,T", 0x5400033c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.lt.s", "M,S,T", 0x5400033c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.lt.ps", "S,T", 0x54000b3c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.lt.ps", "M,S,T", 0x54000b3c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.nge.d", "S,T", 0x5400077c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.nge.d", "M,S,T", 0x5400077c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.nge.s", "S,T", 0x5400037c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.nge.s", "M,S,T", 0x5400037c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.nge.ps", "S,T", 0x54000b7c, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.nge.ps", "M,S,T", 0x54000b7c, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.le.d", "S,T", 0x540007bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.le.d", "M,S,T", 0x540007bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.le.s", "S,T", 0x540003bc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.le.s", "M,S,T", 0x540003bc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.le.ps", "S,T", 0x54000bbc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.le.ps", "M,S,T", 0x54000bbc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngt.d", "S,T", 0x540007fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngt.d", "M,S,T", 0x540007fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngt.s", "S,T", 0x540003fc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngt.s", "M,S,T", 0x540003fc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
+{"c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
+{"cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_b, 0, I1 },
+{"cache", "k,o(b)", 0, (int) M_CACHE_OB, INSN_MACRO, 0, I1 },
+{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I1 },
+{"ceil.l.d", "T,S", 0x5400533b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"ceil.w.d", "T,S", 0x54005b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"ceil.w.s", "T,S", 0x54001b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_t|RD_C1|FP_S, 0, I1 },
+{"cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_t|RD_C1|FP_S, 0, I1 },
+{"cfc2", "t,G", 0x0000cd3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
+{"clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"cop2", "C", 0x00000002, 0xfc000007, CP, 0, I1 },
+{"ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_t|WR_CC|FP_S, 0, I1 },
+{"ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_t|WR_CC|FP_S, 0, I1 },
+{"ctc2", "t,G", 0x0000dd3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
+{"cvt.d.l", "T,S", 0x5400537b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"cvt.d.s", "T,S", 0x5400137b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.d.w", "T,S", 0x5400337b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.l.d", "T,S", 0x5400413b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"cvt.l.s", "T,S", 0x5400013b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.s.l", "T,S", 0x54005b7b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.s.d", "T,S", 0x54001b7b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.s.w", "T,S", 0x54003b7b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"cvt.s.pl", "T,S", 0x5400213b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.s.pu", "T,S", 0x5400293b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.w.d", "T,S", 0x5400493b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"cvt.w.s", "T,S", 0x5400093b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"cvt.ps.s", "D,V,T", 0x54000180, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I1 },
+{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
+{"dadd", "d,v,t", 0x58000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
+{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
+{"daddi", "t,r,.", 0x5800001c, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"daddi", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
+{"daddiu", "t,r,j", 0x5c000000, 0xfc000000, WR_t|RD_s, 0, I3 },
+{"daddu", "d,v,t", 0x58000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
+{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
+{"dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
+{"dclz", "t,s", 0x58005b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
+{"deret", "", 0x0000e37c, 0xffffffff, 0, 0, I1 },
+{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I3 },
+{"dext", "t,r,+A,+C",0x5800002c, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"dextm", "t,r,+A,+G",0x58000024, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"dextu", "t,r,+E,+H",0x58000014, 0xfc00003f, WR_t|RD_s, 0, I3 },
+/* For ddiv, see the comments about div. */
+{"ddiv", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"ddiv", "z,t", 0x5800ab3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 },
+{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 },
+/* For ddivu, see the comments about div. */
+{"ddivu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"ddivu", "z,t", 0x5800bb3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
+{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
+{"di", "", 0x0000477c, 0xffffffff, RD_C0, WR_s, I1 },
+{"di", "s", 0x0000477c, 0xffe0ffff, RD_C0, WR_s, I1 },
+{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I3 },
+{"dins", "t,r,+A,+B",0x5800000c, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"dinsm", "t,r,+A,+F",0x58000004, 0xfc00003f, WR_t|RD_s, 0, I3 },
+{"dinsu", "t,r,+E,+F",0x58000034, 0xfc00003f, WR_t|RD_s, 0, I3 },
+/* The MIPS assembler treats the div opcode with two operands as
+ though the first operand appeared twice (the first operand is both
+ a source and a destination). To get the div machine instruction,
+ you must use an explicit destination of $0. */
+{"div", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"div", "z,t", 0x0000ab3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
+{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
+{"div.d", "D,V,T", 0x540001f0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"div.s", "D,V,T", 0x540000f0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+/* For divu, see the comments about div. */
+{"divu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"divu", "z,t", 0x0000bb3c, 0xfc1fffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
+{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
+{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
+{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
+{"dli", "t,j", 0x30000000, 0xfc1f0000, WR_t, 0, I3 }, /* addiu */
+{"dli", "t,i", 0x50000000, 0xfc1f0000, WR_t, 0, I3 }, /* ori */
+{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 },
+{"dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_t|RD_C0, 0, I3 },
+{"dmfc0", "t,+D", 0x580000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I3 },
+{"dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I3 },
+{"dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I3 },
+{"dmtc0", "t,+D", 0x580002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I3 },
+{"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I3 },
+{"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I3 },
+{"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I3 },
+{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I3 },
+{"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I3 },
+{"dmfc2", "t,G", 0x00006d3c, 0xfc00ffff, WR_t|RD_C2, 0, I3 },
+/*{"dmfc2", "t,G,H", 0x58000283, 0xfc001fff, WR_t|RD_C2, 0, I3 },*/
+{"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I3 },
+/*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_t|WR_C2|WR_CC, 0, I3 },*/
+{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
+{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
+{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 },
+{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 },
+{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 },
+{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 },
+{"dmult", "s,t", 0x58008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"dmultu", "s,t", 0x58009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"dneg", "d,w", 0x58000190, 0xfc1f07ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
+{"dnegu", "d,w", 0x580001d0, 0xfc1f07ff, WR_d|RD_t, 0, I3 }, /* dsubu 0 */
+{"drem", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3 },
+{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
+{"dremu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
+{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
+{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
+{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
+{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
+{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
+{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
+{"dror", "t,r,<", 0x580000c0, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"drorv", "d,t,s", 0x580000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I3 },
+{"dror32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
+{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
+{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
+{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
+{"drotrv", "d,t,s", 0x580000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I3 },
+{"drotr32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsbh", "t,r", 0x58007b3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
+{"dshd", "t,r", 0x5800fb3c, 0xfc00ffff, WR_t|RD_s, 0, I3 },
+{"dsllv", "d,t,s", 0x58000010, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
+{"dsll32", "t,r,<", 0x58000008, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsll", "d,t,s", 0x58000010, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */
+{"dsll", "t,r,>", 0x58000008, 0xfc0007ff, WR_t|RD_s, 0, I3 }, /* dsll32 */
+{"dsll", "t,r,<", 0x58000000, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsrav", "d,t,s", 0x58000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
+{"dsra32", "t,r,<", 0x58000088, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsra", "d,t,s", 0x58000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
+{"dsra", "t,r,>", 0x58000088, 0xfc0007ff, WR_t|RD_s, 0, I3 }, /* dsra32 */
+{"dsra", "t,r,<", 0x58000080, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsrlv", "d,t,s", 0x58000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
+{"dsrl32", "t,r,<", 0x58000048, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsrl", "d,t,s", 0x58000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
+{"dsrl", "t,r,>", 0x58000048, 0xfc0007ff, WR_t|RD_s, 0, I3 }, /* dsrl32 */
+{"dsrl", "t,r,<", 0x58000040, 0xfc0007ff, WR_t|RD_s, 0, I3 },
+{"dsub", "d,v,t", 0x58000190, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
+{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
+{"dsubu", "d,v,t", 0x580001d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
+{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
+{"ei", "", 0x0000577c, 0xffffffff, WR_C0, WR_s, I1 },
+{"ei", "s", 0x0000577c, 0xffe0ffff, WR_C0, WR_s, I1 },
+{"eret", "", 0x0000f37c, 0xffffffff, 0, 0, I1 },
+{"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_t|RD_s, 0, I1 },
+{"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_t|RD_s, 0, I1 },
+{"jr", "mj", 0x4580, 0xffe0, UBD, MOD_mj, I1 },
+{"jr", "s", 0x00000f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr */
+{"jrs", "s", 0x00004f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs */
+{"jraddiusp", "mP", 0x4700, 0xffe0, TRAP, UBR|RD_31|MOD_sp, I1 },
+{"jrc", "mj", 0x45a0, 0xffe0, TRAP, UBR|MOD_mj, I1 },
+{"jr.hb", "s", 0x00001f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr.hb */
+{"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs.hb */
+{"j", "mj", 0x4580, 0xffe0, UBD, MOD_mj, I1 }, /* jr */
+{"j", "s", 0x00000f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jr */
+/* SVR4 PIC code requires special handling for j, so it must be a
+ macro. */
+{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 },
+/* This form of j is used by the disassembler and internally by the
+ assembler, but will never match user input (because the line above
+ will match first). */
+{"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1 },
+{"jalr", "mj", 0x45c0, 0xffe0, UBD|WR_31, MOD_mj|BD32, I1 },
+{"jalr", "my,mj", 0x45c0, 0xffe0, UBD|WR_31, MOD_mj|BD32, I1 },
+{"jalr", "s", 0x03e00f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD32, I1 },
+{"jalr", "t,s", 0x00000f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD32, I1 },
+{"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD32, I1 },
+{"jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD32, I1 },
+{"jalrs", "mj", 0x45e0, 0xffe0, UBD|WR_31, MOD_mj|BD16, I1 },
+{"jalrs", "my,mj", 0x45e0, 0xffe0, UBD|WR_31, MOD_mj|BD16, I1 },
+{"jalrs", "s", 0x03e04f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD16, I1 },
+{"jalrs", "t,s", 0x00004f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD16, I1 },
+{"jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, UBD|RD_s|WR_t, BD16, I1 },
+{"jalrs.hb", "t,s", 0x00005f3c, 0xfc00ffff, UBD|RD_s|WR_t, BD16, I1 },
+/* SVR4 PIC code requires special handling for jal, so it must be a
+ macro. */
+{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 },
+{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 },
+{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 },
+/* This form of jal is used by the disassembler and internally by the
+ assembler, but will never match user input (because the line above
+ will match first). */
+{"jal", "a", 0xf4000000, 0xfc000000, UBD|WR_31, BD32, I1 },
+{"jals", "d,s", 0, (int) M_JALS_2, INSN_MACRO, 0, I1 },
+{"jals", "s", 0, (int) M_JALS_1, INSN_MACRO, 0, I1 },
+{"jals", "a", 0, (int) M_JALS_A, INSN_MACRO, 0, I1 },
+{"jals", "a", 0x74000000, 0xfc000000, UBD|WR_31, BD16, I1 },
+{"jalx", "a", 0xf0000000, 0xfc000000, UBD|WR_31, BD32, I1 },
+{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
+{"lb", "t,o(b)", 0x1c000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
+{"lbu", "md,mG(ml)", 0x0800, 0xfc00, 0, MOD_md|MOD_ml, I1 },
+{"lbu", "t,o(b)", 0x14000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
+{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
+/* The macro has to be first to handle o32 correctly. */
+{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
+{"ld", "t,o(b)", 0xdc000000, 0xfc000000, RD_b|WR_t, 0, I3 },
+{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
+{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
+{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
+{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
+{"ldc2", "E,o(b)", 0, (int) M_LDC2_OB, INSN_MACRO, 0, I1 },
+{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1 },
+{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 }, /* ldc1 */
+{"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_t|RD_b, 0, I3 },
+{"ldl", "t,o(b)", 0, (int) M_LDL_OB, INSN_MACRO, 0, I3 },
+{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
+{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_b, 0, I3 },
+{"ldm", "n,o(b)", 0, (int) M_LDM_OB, INSN_MACRO, 0, I3 },
+{"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3 },
+{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, RD_b|WR_t, 0, I3 },
+{"ldp", "t,o(b)", 0, (int) M_LDP_OB, INSN_MACRO, 0, I3 },
+{"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3 },
+{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_t|RD_b, 0, I3 },
+{"ldr", "t,o(b)", 0, (int) M_LDR_OB, INSN_MACRO, 0, I3 },
+{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
+{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
+{"lh", "t,o(b)", 0x3c000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 },
+{"lhu", "md,mH(ml)", 0x2800, 0xfc00, 0, MOD_md|MOD_ml, I1 },
+{"lhu", "t,o(b)", 0x34000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
+/* li is at the start of the table. */
+{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"ll", "t,~(b)", 0x60003000, 0xfc00f000, RD_b|WR_t, 0, I1 },
+{"ll", "t,o(b)", 0, (int) M_LL_OB, INSN_MACRO, 0, I1 },
+{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1 },
+{"lld", "t,~(b)", 0x60007000, 0xfc00f000, RD_b|WR_t, 0, I3 },
+{"lld", "t,o(b)", 0, (int) M_LLD_OB, INSN_MACRO, 0, I3 },
+{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
+{"lui", "s,u", 0x41a00000, 0xffe00000, 0, WR_s, I1 },
+{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
+{"lw", "md,mJ(ml)", 0x6800, 0xfc00, 0, MOD_md|MOD_ml, I1 },
+{"lw", "mp,mU(ms)", 0x4800, 0xfc00, 0, MOD_mp|MOD_sp, I1 }, /* lwsp */
+{"lw", "md,mA(ma)", 0x6400, 0xfc00, 0, MOD_md|RD_gp, I1 }, /* lwgp */
+{"lw", "t,o(b)", 0xfc000000, 0xfc000000, RD_b|WR_t, 0, I1 },
+{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
+{"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 },
+{"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 },
+{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
+{"lwc2", "E,o(b)", 0, (int) M_LWC2_OB, INSN_MACRO, 0, I1 },
+{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
+{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
+{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 },
+{"lwl", "t,o(b)", 0, (int) M_LWL_OB, INSN_MACRO, 0, I1 },
+{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
+{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
+{"lcache", "t,o(b)", 0, (int) M_LWL_OB, INSN_MACRO, 0, I1 },
+{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
+{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, TRAP, MOD_sp, I1 },
+{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_b|TRAP, 0, I1 },
+{"lwm", "n,o(b)", 0, (int) M_LWM_OB, INSN_MACRO, 0, I1 },
+{"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1 },
+{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, RD_b|WR_t|TRAP, 0, I1 },
+{"lwp", "t,o(b)", 0, (int) M_LWP_OB, INSN_MACRO, 0, I1 },
+{"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1 },
+{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 },
+{"lwr", "t,o(b)", 0, (int) M_LWR_OB, INSN_MACRO, 0, I1 },
+{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
+{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, RD_b|WR_t, 0, I3 },
+{"lwu", "t,o(b)", 0, (int) M_LWU_OB, INSN_MACRO, 0, I3 },
+{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
+{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_D|RD_t|RD_b|FP_S, 0, I1 },
+{"flush", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
+{"flush", "t,o(b)", 0, (int) M_LWR_OB, INSN_MACRO, 0, I1 },
+{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
+{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, RD_b|RD_t|WR_d, 0, I1 },
+{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
+{"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_t|RD_C0, 0, I1 },
+{"mfc0", "t,+D", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 },
+{"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 },
+{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I1 },
+{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I1 },
+{"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
+{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_t|RD_S|FP_D, 0, I1 },
+{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_t|RD_S|FP_D, 0, I1 },
+{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
+{"mfhi", "mj", 0x4600, 0xffe0, RD_HI, MOD_mj, I1 },
+{"mfhi", "s", 0x00000d7c, 0xffe0ffff, RD_HI, WR_s, I1 },
+{"mflo", "mj", 0x4640, 0xffe0, RD_LO, MOD_mj, I1 },
+{"mflo", "s", 0x00001d7c, 0xffe0ffff, RD_LO, WR_s, I1 },
+{"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"movep", "mh,mi,mm,mn", 0x8400, 0xfc01, TRAP, MOD_mhi|MOD_mm|MOD_mn, I1 },
+{"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_t|RD_s|RD_CC|FP_S|FP_D, 0, I1 },
+{"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
+{"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_T|RD_S|RD_CC|FP_S, 0, I1 },
+{"movf.ps", "T,S,M", 0x54000420, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
+{"movn", "d,v,t", 0x00000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"movn.d", "D,S,t", 0x54000138, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
+{"movn.s", "D,S,t", 0x54000038, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S, 0, I1 },
+{"movn.ps", "D,S,t", 0x54000238, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
+{"movt", "t,s,M", 0x5400097b, 0xfc001fff, WR_t|RD_s|RD_CC|FP_S|FP_D, 0, I1 },
+{"movt.d", "T,S,M", 0x54000260, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
+{"movt.s", "T,S,M", 0x54000060, 0xfc001fff, WR_T|RD_S|RD_CC|FP_S, 0, I1 },
+{"movt.ps", "T,S,M", 0x54000460, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
+{"movz", "d,v,t", 0x00000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"movz.d", "D,S,t", 0x54000178, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
+{"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S, 0, I1 },
+{"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
+{"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
+{"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc0", "t,+D", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I1 },
+{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I1 },
+{"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
+{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 },
+{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 },
+{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
+{"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_s|WR_HI, 0, I1 },
+{"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_s|WR_LO, 0, I1 },
+{"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I1 },
+{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
+{"mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"mul.s", "D,V,T", 0x540000b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"mul.ps", "D,V,T", 0x540002b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
+{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
+{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
+{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
+{"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"neg", "d,w", 0x00000190, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
+{"negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
+{"neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"neg.s", "T,V", 0x54000b7b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"neg.ps", "T,V", 0x54004b7b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"nmadd.d", "D,R,S,T", 0x5400000a, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"nmadd.s", "D,R,S,T", 0x54000002, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
+{"nmadd.ps", "D,R,S,T", 0x54000012, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"nmsub.d", "D,R,S,T", 0x5400002a, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+{"nmsub.s", "D,R,S,T", 0x54000022, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
+{"nmsub.ps", "D,R,S,T", 0x54000032, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
+/* nop is at the start of the table. */
+{"not", "mf,mg", 0x4400, 0xffc0, 0, MOD_mf|MOD_mg, I1 }, /* put not before nor */
+{"not", "d,v", 0x000002d0, 0xffe007ff, WR_d|RD_s|RD_t, 0, I1 }, /* nor d,s,0 */
+{"nor", "mf,mz,mg", 0x4400, 0xffc0, 0, MOD_mf|MOD_mg, I1 }, /* not */
+{"nor", "mf,mg,mz", 0x4400, 0xffc0, 0, MOD_mf|MOD_mg, I1 }, /* not */
+{"nor", "d,v,t", 0x000002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
+{"or", "mp,mj,mz", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"or", "mp,mz,mj", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"or", "mf,mt,mg", 0x44c0, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"or", "mf,mg,mx", 0x44c0, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"or", "d,v,t", 0x00000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
+{"ori", "mp,mj,mZ", 0x0c00, 0xfc00, 0, MOD_mp|MOD_mj, I1 }, /* move */
+{"ori", "t,r,i", 0x50000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"pll.ps", "D,V,T", 0x54000080, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"plu.ps", "D,V,T", 0x540000c0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"pul.ps", "D,V,T", 0x54000100, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"puu.ps", "D,V,T", 0x54000140, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+/* pref is at the start of the table. */
+{"recip.d", "T,S", 0x5400523b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"recip.s", "T,S", 0x5400123b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"rem", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
+{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 },
+{"remu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
+{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 },
+{"rdhwr", "t,K", 0x00006b3c, 0xfc00ffff, 0, WR_t, I1 },
+{"rdpgpr", "t,r", 0x0000e17c, 0xfc00ffff, WR_t, 0, I1 },
+{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
+{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
+{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
+{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
+{"ror", "t,r,<", 0x000000c0, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+{"rorv", "d,t,s", 0x000000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I1 },
+{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
+{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
+{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
+{"rotr", "t,r,<", 0x000000c0, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+{"rotrv", "d,t,s", 0x000000d0, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I1 },
+{"round.l.d", "T,S", 0x5400733b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"round.l.s", "T,S", 0x5400333b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"round.w.d", "T,S", 0x54007b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"round.w.s", "T,S", 0x54003b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"rsqrt.d", "T,S", 0x5400423b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"rsqrt.s", "T,S", 0x5400023b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"sb", "mq,mL(ml)", 0x8800, 0xfc00, SM, MOD_mq|MOD_ml, I1 },
+{"sb", "t,o(b)", 0x18000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
+{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
+{"sc", "t,~(b)", 0x6000b000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I1 },
+{"sc", "t,o(b)", 0, (int) M_SC_OB, INSN_MACRO, 0, I1 },
+{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I1 },
+{"scd", "t,~(b)", 0x6000f000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I3 },
+{"scd", "t,o(b)", 0, (int) M_SCD_OB, INSN_MACRO, 0, I3 },
+{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
+/* The macro has to be first to handle o32 correctly. */
+{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
+{"sd", "t,o(b)", 0xd8000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
+{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
+{"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1 },
+{"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1 },
+{"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1 },
+{"sdbbp", "B", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1 },
+{"sdc1", "T,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 },
+{"sdc1", "E,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 },
+{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
+{"sdc2", "E,o(b)", 0, (int) M_SDC2_OB, INSN_MACRO, 0, I1 },
+{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I1 },
+{"s.d", "T,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 }, /* sdc1 */
+{"s.d", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
+{"sdl", "t,~(b)", 0x6000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
+{"sdl", "t,o(b)", 0, (int) M_SDL_OB, INSN_MACRO, 0, I3 },
+{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
+{"sdm", "n,~(b)", 0x2000f000, 0xfc00f000, SM|RD_b, 0, I3 },
+{"sdm", "n,o(b)", 0, (int) M_SDM_OB, INSN_MACRO, 0, I3 },
+{"sdm", "n,A(b)", 0, (int) M_SDM_AB, INSN_MACRO, 0, I3 },
+{"sdp", "t,~(b)", 0x2000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
+{"sdp", "t,o(b)", 0, (int) M_SDP_OB, INSN_MACRO, 0, I3 },
+{"sdp", "t,A(b)", 0, (int) M_SDP_AB, INSN_MACRO, 0, I3 },
+{"sdr", "t,~(b)", 0x6000d000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
+{"sdr", "t,o(b)", 0, (int) M_SDR_OB, INSN_MACRO, 0, I3 },
+{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
+{"sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, SM|RD_t|RD_b|FP_D, RD_D, I1 },
+{"seb", "t,r", 0x00002b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"seh", "t,r", 0x00003b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
+{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
+{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
+{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
+{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 },
+{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 },
+{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 },
+{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 },
+{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 },
+{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 },
+{"sh", "mq,mH(ml)", 0xa800, 0xfc00, SM, MOD_mq|MOD_ml, I1 },
+{"sh", "t,o(b)", 0x38000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
+{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 },
+{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
+{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
+{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
+{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
+{"sllv", "d,t,s", 0x00000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"sll", "md,mc,mM", 0x2400, 0xfc01, 0, MOD_md|MOD_mc, I1 },
+{"sll", "d,w,s", 0x00000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, /* sllv */
+{"sll", "t,r,<", 0x00000000, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+{"slt", "d,v,t", 0x00000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
+{"slti", "t,r,j", 0x90000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"sltiu", "t,r,j", 0xb0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"sltu", "d,v,t", 0x00000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
+{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
+{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
+{"sqrt.d", "T,S", 0x54004a3b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"sqrt.s", "T,S", 0x54000a3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"srav", "d,t,s", 0x00000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
+{"sra", "d,w,s", 0x00000090, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
+{"sra", "t,r,<", 0x00000080, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+{"srlv", "d,t,s", 0x00000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
+{"srl", "md,mc,mM", 0x2401, 0xfc01, 0, MOD_md|MOD_mc, I1 },
+{"srl", "d,w,s", 0x00000050, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
+{"srl", "t,r,<", 0x00000040, 0xfc0007ff, WR_t|RD_s, 0, I1 },
+/* ssnop is at the start of the table. */
+{"sub", "d,v,t", 0x00000190, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
+{"sub.d", "D,V,T", 0x54000170, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"sub.s", "D,V,T", 0x54000070, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"sub.ps", "D,V,T", 0x54000270, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"subu", "md,me,ml", 0x0401, 0xfc01, 0, MOD_md|MOD_me|MOD_ml, I1 },
+{"subu", "d,v,t", 0x000001d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
+{"suxc1", "D,t(b)", 0x54000188, 0xfc0007ff, SM|RD_t|RD_b|FP_D, RD_D, I1 },
+{"sw", "mq,mJ(ml)", 0xe800, 0xfc00, SM, MOD_mq|MOD_ml, I1 },
+{"sw", "mp,mU(ms)", 0xc800, 0xfc00, SM, MOD_mp|MOD_sp, I1 }, /* swsp */
+{"sw", "t,o(b)", 0xf8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
+{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
+{"swc1", "T,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
+{"swc1", "E,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
+{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"swc2", "E,~(b)", 0x20008000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
+{"swc2", "E,o(b)", 0, (int) M_SWC2_OB, INSN_MACRO, 0, I1 },
+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
+{"s.s", "T,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
+{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"swl", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 },
+{"swl", "t,o(b)", 0, (int) M_SWL_OB, INSN_MACRO, 0, I1 },
+{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
+{"scache", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 }, /* same */
+{"scache", "t,o(b)", 0, (int) M_SWL_OB, INSN_MACRO, 0, I1 },
+{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
+{"swm", "mN,mJ(ms)", 0x4540, 0xffc0, TRAP, MOD_sp, I1 },
+{"swm", "n,~(b)", 0x2000d000, 0xfc00f000, SM|RD_b|TRAP, 0, I1 },
+{"swm", "n,o(b)", 0, (int) M_SWM_OB, INSN_MACRO, 0, I1 },
+{"swm", "n,A(b)", 0, (int) M_SWM_AB, INSN_MACRO, 0, I1 },
+{"swp", "t,~(b)", 0x20009000, 0xfc00f000, SM|RD_t|RD_b|TRAP, 0, I1 },
+{"swp", "t,o(b)", 0, (int) M_SWP_OB, INSN_MACRO, 0, I1 },
+{"swp", "t,A(b)", 0, (int) M_SWP_AB, INSN_MACRO, 0, I1 },
+{"swr", "t,~(b)", 0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 },
+{"swr", "t,o(b)", 0, (int) M_SWR_OB, INSN_MACRO, 0, I1 },
+{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
+{"invalidate", "t,~(b)",0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 }, /* same */
+{"invalidate", "t,o(b)",0, (int) M_SWR_OB, INSN_MACRO, 0, I1 },
+{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
+{"swxc1", "D,t(b)", 0x54000048, 0xfc0007ff, SM|RD_t|RD_b|FP_S, RD_D, I1 },
+{"sync_acquire", "", 0x00116b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync_mb", "", 0x00106b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync_release", "", 0x00126b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync_rmb", "", 0x00136b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync_wmb", "", 0x00046b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync", "", 0x00006b7c, 0xffffffff, INSN_SYNC, 0, I1 },
+{"sync", "1", 0x00006b7c, 0xffe0ffff, INSN_SYNC, 0, I1 },
+{"synci", "o(b)", 0x42000000, 0xffe00000, SM|RD_b, 0, I1 },
+{"syscall", "", 0x00008b7c, 0xffffffff, TRAP, 0, I1 },
+{"syscall", "B", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1 },
+{"teqi", "s,j", 0x41c00000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"teq", "s,t", 0x0000003c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"teq", "s,t,|", 0x0000003c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"teq", "s,j", 0x41c00000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* teqi */
+{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I1 },
+{"tgei", "s,j", 0x41200000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tge", "s,t", 0x0000023c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tge", "s,t,|", 0x0000023c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tge", "s,j", 0x41200000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tgei */
+{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I1 },
+{"tgeiu", "s,j", 0x41600000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tgeu", "s,t", 0x0000043c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tgeu", "s,t,|", 0x0000043c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tgeu", "s,j", 0x41600000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tgeiu */
+{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I1 },
+{"tlbp", "", 0x0000037c, 0xffffffff, INSN_TLB, 0, I1 },
+{"tlbr", "", 0x0000137c, 0xffffffff, INSN_TLB, 0, I1 },
+{"tlbwi", "", 0x0000237c, 0xffffffff, INSN_TLB, 0, I1 },
+{"tlbwr", "", 0x0000337c, 0xffffffff, INSN_TLB, 0, I1 },
+{"tlti", "s,j", 0x41000000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tlt", "s,t", 0x0000083c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tlt", "s,t,|", 0x0000083c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tlt", "s,j", 0x41000000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tlti */
+{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I1 },
+{"tltiu", "s,j", 0x41400000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tltu", "s,t", 0x00000a3c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tltu", "s,t,|", 0x00000a3c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tltu", "s,j", 0x41400000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tltiu */
+{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I1 },
+{"tnei", "s,j", 0x41800000, 0xffe00000, RD_s|TRAP, 0, I1 },
+{"tne", "s,t", 0x00000c3c, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I1 },
+{"tne", "s,t,|", 0x00000c3c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 },
+{"tne", "s,j", 0x41800000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tnei */
+{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I1 },
+{"trunc.l.d", "T,S", 0x5400633b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"trunc.l.s", "T,S", 0x5400233b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"trunc.w.d", "T,S", 0x54006b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
+{"trunc.w.s", "T,S", 0x54002b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
+{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
+{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
+{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
+{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
+{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
+{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
+{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
+{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I1 },
+{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I1 },
+{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
+{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
+{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
+{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
+{"wait", "", 0x0000937c, 0xffffffff, TRAP, 0, I1 },
+{"wait", "B", 0x0000937c, 0xfc00ffff, TRAP, 0, I1 },
+{"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_s, 0, I1 },
+{"wsbh", "t,r", 0x00007b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
+{"xor", "mf,mt,mg", 0x4440, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"xor", "mf,mg,mx", 0x4440, 0xffc0, 0, MOD_mf|MOD_mg, I1 },
+{"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
+{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+};
+
+const int bfd_micromips_num_opcodes =
+ ((sizeof micromips_opcodes) / (sizeof (micromips_opcodes[0])));
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index c38a7e1..75f9bb7 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -57,6 +57,91 @@ static const unsigned int mips16_to_32_reg_map[] =
16, 17, 2, 3, 4, 5, 6, 7
};
+/* The microMIPS registers with type b. */
+#define micromips_to_32_reg_b_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type c. */
+#define micromips_to_32_reg_c_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type d. */
+#define micromips_to_32_reg_d_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type e. */
+#define micromips_to_32_reg_e_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type f. */
+#define micromips_to_32_reg_f_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type g. */
+#define micromips_to_32_reg_g_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type h. */
+static const unsigned int micromips_to_32_reg_h_map[] =
+{
+ 5, 5, 6, 4, 4, 4, 4, 4
+};
+
+/* The microMIPS registers with type i. */
+static const unsigned int micromips_to_32_reg_i_map[] =
+{
+ 6, 7, 7, 21, 22, 5, 6, 7
+};
+
+/* The microMIPS registers with type j: 32 registers. */
+
+/* The microMIPS registers with type l. */
+#define micromips_to_32_reg_l_map mips16_to_32_reg_map
+
+/* The microMIPS registers with type m. */
+static const unsigned int micromips_to_32_reg_m_map[] =
+{
+ 0, 17, 2, 3, 16, 18, 19, 20
+};
+
+/* The microMIPS registers with type n. */
+#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
+
+/* The microMIPS registers with type p: 32 registers. */
+
+/* The microMIPS registers with type q. */
+static const unsigned int micromips_to_32_reg_q_map[] =
+{
+ 0, 17, 2, 3, 4, 5, 6, 7
+};
+
+/* reg type s is $29. */
+
+/* reg type t is the same as the last register. */
+
+/* reg type y is $31. */
+
+/* reg type z is $0. */
+
+/* micromips imm B type. */
+static const int micromips_imm_b_map[8] =
+{
+ 1, 4, 8, 12, 16, 20, 24, -1
+};
+
+/* micromips imm C type. */
+static const int micromips_imm_c_map[16] =
+{
+ 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
+};
+
+/* micromips imm D type: (-512..511)<<1. */
+/* micromips imm E type: (-64..63)<<1. */
+/* micromips imm F type: (0..63). */
+/* micromips imm G type: (-1..14). */
+/* micromips imm H type: (0..15)<<1. */
+/* micromips imm I type: (-1..126). */
+/* micromips imm J type: (0..15)<<2. */
+/* micromips imm L type: (0..15). */
+/* micromips imm M type: (1..8). */
+/* micromips imm W type: (0..63)<<2. */
+/* micromips imm X type: (-8..7). */
+/* micromips imm Y type: (-258..-3, 2..257)<<2. */
+
#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
@@ -537,6 +622,7 @@ const struct mips_arch_choice mips_arch_choices[] =
values. */
static int mips_processor;
static int mips_isa;
+static int micromips_ase;
static const char * const *mips_gpr_names;
static const char * const *mips_fpr_names;
static const char * const *mips_cp0_names;
@@ -619,15 +705,28 @@ is_newabi (Elf_Internal_Ehdr *header)
return 0;
}
+/* Check if the object has microMIPS ASE code. */
+
+static int
+is_micromips (Elf_Internal_Ehdr *header)
+{
+ if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
+ return 1;
+
+ return 0;
+}
+
static void
set_default_mips_dis_options (struct disassemble_info *info)
{
const struct mips_arch_choice *chosen_arch;
- /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
- and numeric FPR, CP0 register, and HWR names. */
+ /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code
+ is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR,
+ CP0 register, and HWR names. */
mips_isa = ISA_MIPS3;
- mips_processor = CPU_R3000;
+ mips_processor = CPU_R3000;
+ micromips_ase = 0;
mips_gpr_names = mips_gpr_names_oldabi;
mips_fpr_names = mips_fpr_names_numeric;
mips_cp0_names = mips_cp0_names_numeric;
@@ -636,14 +735,17 @@ set_default_mips_dis_options (struct disassemble_info *info)
mips_hwr_names = mips_hwr_names_numeric;
no_aliases = 0;
- /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
+ /* Update settings according to the ELF file header flags. */
if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
{
Elf_Internal_Ehdr *header;
header = elf_elfheader (info->section->owner);
+ /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
if (is_newabi (header))
mips_gpr_names = mips_gpr_names_newabi;
+ /* If a microMIPS binary, then don't use MIPS16 bindings. */
+ micromips_ase = is_micromips (header);
}
/* Set ISA, architecture, and cp0 register names as best we can. */
@@ -2141,6 +2243,723 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
return length;
}
+/* Disassemble microMIPS instructions. */
+
+static int
+print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
+{
+ const fprintf_ftype iprintf = info->fprintf_func;
+ const struct mips_opcode *op, *opend;
+ unsigned int lsb, msbd, msb;
+ void *is = info->stream;
+ unsigned int regno;
+ bfd_byte buffer[2];
+ int lastregno = 0;
+ int higher;
+ int length;
+ int status;
+ int delta;
+ int immed;
+ int insn;
+
+ lsb = 0;
+
+ info->bytes_per_chunk = 2;
+ info->display_endian = info->endian;
+ info->insn_info_valid = 1;
+ info->branch_delay_insns = 0;
+ info->data_size = 0;
+ info->insn_type = dis_nonbranch;
+ info->target = 0;
+ info->target2 = 0;
+
+ status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, memaddr, info);
+ return -1;
+ }
+
+ length = 2;
+
+ if (info->endian == BFD_ENDIAN_BIG)
+ insn = bfd_getb16 (buffer);
+ else
+ insn = bfd_getl16 (buffer);
+
+ if ((insn & 0xfc00) == 0x7c00)
+ {
+ /* This is a 48-bit microMIPS instruction. */
+ higher = insn;
+
+ status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
+ if (status != 0)
+ {
+ iprintf (is, "micromips 0x%x", higher);
+ (*info->memory_error_func) (status, memaddr + 2, info);
+ return -1;
+ }
+ if (info->endian == BFD_ENDIAN_BIG)
+ insn = bfd_getb16 (buffer);
+ else
+ insn = bfd_getl16 (buffer);
+ higher = (higher << 16) | insn;
+
+ status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
+ if (status != 0)
+ {
+ iprintf (is, "micromips 0x%x", higher);
+ (*info->memory_error_func) (status, memaddr + 4, info);
+ return -1;
+ }
+ if (info->endian == BFD_ENDIAN_BIG)
+ insn = bfd_getb16 (buffer);
+ else
+ insn = bfd_getl16 (buffer);
+ iprintf (is, "0x%x%04x (48-bit insn)", higher, insn);
+
+ info->insn_type = dis_noninsn;
+ return 6;
+ }
+ else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
+ {
+ /* This is a 32-bit microMIPS instruction. */
+ higher = insn;
+
+ status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
+ if (status != 0)
+ {
+ iprintf (is, "micromips 0x%x", higher);
+ (*info->memory_error_func) (status, memaddr + 2, info);
+ return -1;
+ }
+
+ if (info->endian == BFD_ENDIAN_BIG)
+ insn = bfd_getb16 (buffer);
+ else
+ insn = bfd_getl16 (buffer);
+
+ insn = insn | (higher << 16);
+
+ length += 2;
+ }
+
+ /* FIXME: Should probably use a hash table on the major opcode here. */
+
+#define GET_OP(insn, field) \
+ (((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
+ opend = micromips_opcodes + bfd_micromips_num_opcodes;
+ for (op = micromips_opcodes; op < opend; op++)
+ {
+ if (op->pinfo != INSN_MACRO
+ && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
+ && (insn & op->mask) == op->match
+ && ((length == 2 && (op->mask & 0xffff0000) == 0)
+ || (length == 4 && (op->mask & 0xffff0000) != 0)))
+ {
+ const char *s;
+
+ iprintf (is, "%s", op->name);
+ if (op->args[0] != '\0')
+ iprintf (is, "\t");
+
+ for (s = op->args; *s != '\0'; s++)
+ {
+ switch (*s)
+ {
+ case ',':
+ case '(':
+ case ')':
+ iprintf (is, "%c", *s);
+ break;
+
+ case '.':
+ delta = GET_OP (insn, OFFSET10);
+ if (delta & 0x200)
+ delta |= ~0x3ff;
+ iprintf (is, "%d", delta);
+ break;
+
+ case '1':
+ iprintf (is, "0x%lx", GET_OP (insn, STYPE));
+ break;
+
+ case '<':
+ iprintf (is, "0x%lx", GET_OP (insn, SHAMT));
+ break;
+
+ case '|':
+ iprintf (is, "0x%lx", GET_OP (insn, TRAP));
+ break;
+
+ case '~':
+ delta = GET_OP (insn, OFFSET12);
+ if (delta & 0x800)
+ delta |= ~0x7ff;
+ iprintf (is, "%d", delta);
+ break;
+
+ case 'a':
+ if (strcmp (op->name, "jalx") == 0)
+ info->target = (((memaddr + 4) & ~(bfd_vma) 0x0fffffff)
+ | (GET_OP (insn, TARGET) << 2));
+ else
+ info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
+ | ((GET_OP (insn, TARGET)) << 1));
+ /* For gdb disassembler, force odd address on jalx. */
+ if (info->flavour == bfd_target_unknown_flavour
+ && strcmp (op->name, "jalx") == 0)
+ info->target |= 1;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'b':
+ case 'r':
+ case 's':
+ case 'v':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS)]);
+ break;
+
+ case 'c':
+ iprintf (is, "0x%lx", GET_OP (insn, CODE));
+ break;
+
+ case 'd':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RD)]);
+ break;
+
+ case 'h':
+ iprintf (is, "0x%lx", GET_OP (insn, PREFX));
+ break;
+
+ case 'i':
+ case 'u':
+ iprintf (is, "0x%lx", GET_OP (insn, IMMEDIATE));
+ break;
+
+ case 'j': /* Same as i, but sign-extended. */
+ case 'o':
+ delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
+ iprintf (is, "%d", delta);
+ break;
+
+ case 'k':
+ iprintf (is, "0x%x", GET_OP (insn, CACHE));
+ break;
+
+ case 'n':
+ {
+ int s_reg_encode;
+
+ immed = GET_OP (insn, RT);
+ s_reg_encode = immed & 0xf;
+ if (s_reg_encode != 0)
+ {
+ if (s_reg_encode == 1)
+ iprintf (is, "%s", mips_gpr_names[16]);
+ else if (s_reg_encode < 9)
+ iprintf (is, "%s-%s",
+ mips_gpr_names[16],
+ mips_gpr_names[15 + s_reg_encode]);
+ else if (s_reg_encode == 9)
+ iprintf (is, "%s-%s,%s",
+ mips_gpr_names[16],
+ mips_gpr_names[23],
+ mips_gpr_names[30]);
+ else
+ iprintf (is, "UNKNOWN");
+ }
+
+ if (immed & 0x10) /* For ra. */
+ {
+ if (s_reg_encode == 0)
+ iprintf (is, "%s", mips_gpr_names[31]);
+ else
+ iprintf (is, ",%s", mips_gpr_names[31]);
+ }
+ break;
+ }
+
+ case 'p':
+ /* Sign-extend the displacement. */
+ delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
+ info->target = (delta << 1) + memaddr + length;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'q':
+ iprintf (is, "0x%lx", GET_OP (insn, CODE2));
+ break;
+
+ case 't':
+ case 'w':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RT)]);
+ break;
+
+ case 'y':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS3)]);
+ break;
+
+ case 'z':
+ iprintf (is, "%s", mips_gpr_names[0]);
+ break;
+
+ case 'B':
+ iprintf (is, "0x%lx", GET_OP (insn, CODE10));
+ break;
+
+ case 'C':
+ iprintf (is, "0x%lx", GET_OP (insn, COPZ));
+ break;
+
+ case 'D':
+ iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FD)]);
+ break;
+
+ case 'E':
+ /* Coprocessor register for lwcN instructions, et al.
+
+ Note that there is no load/store cp0 instructions, and
+ that FPU (cp1) instructions disassemble this field using
+ 'T' format. Therefore, until we gain understanding of
+ cp2 register names, we can simply print the register
+ numbers. */
+ iprintf (is, "$%ld", GET_OP (insn, RT));
+ break;
+
+ case 'G':
+ /* Coprocessor register for mtcN instructions, et al. Note
+ that FPU (cp1) instructions disassemble this field using
+ 'S' format. Therefore, we only need to worry about cp0,
+ cp2, and cp3.
+ The microMIPS encoding does not have a coprocessor
+ identifier field as such, so we must work out the
+ coprocessor number by looking at the opcode. */
+ switch (insn
+ & ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
+ | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)))
+ {
+ case 0x000000fc: /* mfc0 */
+ case 0x000002fc: /* mtc0 */
+ case 0x580000fc: /* dmfc0 */
+ case 0x580002fc: /* dmtc0 */
+ iprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]);
+ break;
+ default:
+ iprintf (is, "$%ld", GET_OP (insn, RS));
+ break;
+ }
+ break;
+
+ case 'H':
+ iprintf (is, "%ld", GET_OP (insn, SEL));
+ break;
+
+ case 'K':
+ iprintf (is, "%s", mips_hwr_names[GET_OP (insn, RS)]);
+ break;
+
+ case 'M':
+ iprintf (is, "$fcc%ld", GET_OP (insn, CCC));
+ break;
+
+ case 'N':
+ iprintf (is,
+ (op->pinfo & (FP_D | FP_S)) != 0
+ ? "$fcc%ld" : "$cc%ld",
+ GET_OP (insn, BCC));
+ break;
+
+ case 'R':
+ iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FR)]);
+ break;
+
+ case 'S':
+ case 'V':
+ iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FS)]);
+ break;
+
+ case 'T':
+ iprintf (is, "%s", mips_fpr_names[GET_OP (insn, FT)]);
+ break;
+
+ case '+':
+ /* Extension character; switch for second char. */
+ s++;
+ switch (*s)
+ {
+ case 'A':
+ lsb = GET_OP (insn, EXTLSB);
+ iprintf (is, "0x%x", lsb);
+ break;
+
+ case 'B':
+ msb = GET_OP (insn, INSMSB);
+ iprintf (is, "0x%x", msb - lsb + 1);
+ break;
+
+ case 'C':
+ case 'H':
+ msbd = GET_OP (insn, EXTMSBD);
+ iprintf (is, "0x%x", msbd + 1);
+ break;
+
+ case 'D':
+ {
+ const struct mips_cp0sel_name *n;
+ unsigned int cp0reg, sel;
+
+ cp0reg = GET_OP (insn, RS);
+ sel = GET_OP (insn, SEL);
+
+ /* CP0 register including 'sel' code for mtcN
+ (et al.), to be printed textually if known.
+ If not known, print both CP0 register name and
+ sel numerically since CP0 register with sel 0 may
+ have a name unrelated to register being printed. */
+ n = lookup_mips_cp0sel_name (mips_cp0sel_names,
+ mips_cp0sel_names_len,
+ cp0reg, sel);
+ if (n != NULL)
+ iprintf (is, "%s", n->name);
+ else
+ iprintf (is, "$%d,%d", cp0reg, sel);
+ break;
+ }
+
+ case 'E':
+ lsb = GET_OP (insn, EXTLSB) + 32;
+ iprintf (is, "0x%x", lsb);
+ break;
+
+ case 'F':
+ msb = GET_OP (insn, INSMSB) + 32;
+ iprintf (is, "0x%x", msb - lsb + 1);
+ break;
+
+ case 'G':
+ msbd = GET_OP (insn, EXTMSBD) + 32;
+ iprintf (is, "0x%x", msbd + 1);
+ break;
+
+ default:
+ /* xgettext:c-format */
+ iprintf (is,
+ _("# internal disassembler error, "
+ "unrecognized modifier (+%c)"),
+ *s);
+ abort ();
+ }
+ break;
+
+ case 'm':
+ /* Extension character; switch for second char. */
+ s++;
+ switch (*s)
+ {
+ case 'a': /* global pointer. */
+ iprintf (is, "%s", mips_gpr_names[28]);
+ break;
+
+ case 'b':
+ regno = micromips_to_32_reg_b_map[GET_OP (insn, MB)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'c':
+ regno = micromips_to_32_reg_c_map[GET_OP (insn, MC)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'd':
+ regno = micromips_to_32_reg_d_map[GET_OP (insn, MD)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'e':
+ regno = micromips_to_32_reg_e_map[GET_OP (insn, ME)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'f':
+ /* Save lastregno for "mt" to print out later. */
+ lastregno = micromips_to_32_reg_f_map[GET_OP (insn, MF)];
+ iprintf (is, "%s", mips_gpr_names[lastregno]);
+ break;
+
+ case 'g':
+ regno = micromips_to_32_reg_g_map[GET_OP (insn, MG)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'h':
+ regno = micromips_to_32_reg_h_map[GET_OP (insn, MH)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'i':
+ regno = micromips_to_32_reg_i_map[GET_OP (insn, MI)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'j':
+ iprintf (is, "%s", mips_gpr_names[GET_OP (insn, MJ)]);
+ break;
+
+ case 'l':
+ regno = micromips_to_32_reg_l_map[GET_OP (insn, ML)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'm':
+ regno = micromips_to_32_reg_m_map[GET_OP (insn, MM)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'n':
+ regno = micromips_to_32_reg_n_map[GET_OP (insn, MN)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'p':
+ /* Save lastregno for "mt" to print out later. */
+ lastregno = GET_OP (insn, MP);
+ iprintf (is, "%s", mips_gpr_names[lastregno]);
+ break;
+
+ case 'q':
+ regno = micromips_to_32_reg_q_map[GET_OP (insn, MQ)];
+ iprintf (is, "%s", mips_gpr_names[regno]);
+ break;
+
+ case 'r': /* program counter. */
+ iprintf (is, "$pc");
+ break;
+
+ case 's': /* stack pointer. */
+ lastregno = 29;
+ iprintf (is, "%s", mips_gpr_names[29]);
+ break;
+
+ case 't':
+ iprintf (is, "%s", mips_gpr_names[lastregno]);
+ break;
+
+ case 'z': /* $0. */
+ iprintf (is, "%s", mips_gpr_names[0]);
+ break;
+
+ case 'A':
+ /* Sign-extend the immediate. */
+ immed = ((GET_OP (insn, IMMA) ^ 0x40) - 0x40) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'B':
+ immed = micromips_imm_b_map[GET_OP (insn, IMMB)];
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'C':
+ immed = micromips_imm_c_map[GET_OP (insn, IMMC)];
+ iprintf (is, "0x%lx", immed);
+ break;
+
+ case 'D':
+ /* Sign-extend the displacement. */
+ delta = (GET_OP (insn, IMMD) ^ 0x200) - 0x200;
+ info->target = (delta << 1) + memaddr + length;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'E':
+ /* Sign-extend the displacement. */
+ delta = (GET_OP (insn, IMME) ^ 0x40) - 0x40;
+ info->target = (delta << 1) + memaddr + length;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'F':
+ immed = GET_OP (insn, IMMF);
+ iprintf (is, "0x%x", immed);
+ break;
+
+ case 'G':
+ immed = (insn >> MICROMIPSOP_SH_IMMG) + 1;
+ immed = (immed & MICROMIPSOP_MASK_IMMG) - 1;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'H':
+ immed = GET_OP (insn, IMMH) << 1;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'I':
+ immed = (insn >> MICROMIPSOP_SH_IMMI) + 1;
+ immed = (immed & MICROMIPSOP_MASK_IMMI) - 1;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'J':
+ immed = GET_OP (insn, IMMJ) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'L':
+ immed = GET_OP (insn, IMML);
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'M':
+ immed = (insn >> MICROMIPSOP_SH_IMMM) - 1;
+ immed = (immed & MICROMIPSOP_MASK_IMMM) + 1;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'N':
+ immed = GET_OP (insn, IMMN);
+ if (immed == 0)
+ iprintf (is, "%s,%s",
+ mips_gpr_names[16],
+ mips_gpr_names[31]);
+ else
+ iprintf (is, "%s-%s,%s",
+ mips_gpr_names[16],
+ mips_gpr_names[16 + immed],
+ mips_gpr_names[31]);
+ break;
+
+ case 'O':
+ immed = GET_OP (insn, IMMO);
+ iprintf (is, "0x%x", immed);
+ break;
+
+ case 'P':
+ immed = GET_OP (insn, IMMP) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'Q':
+ /* Sign-extend the immediate. */
+ immed = (GET_OP (insn, IMMQ) ^ 0x400000) - 0x400000;
+ immed <<= 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'U':
+ immed = GET_OP (insn, IMMU) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'W':
+ immed = GET_OP (insn, IMMW) << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'X':
+ /* Sign-extend the immediate. */
+ immed = (GET_OP (insn, IMMX) ^ 0x8) - 0x8;
+ iprintf (is, "%d", immed);
+ break;
+
+ case 'Y':
+ /* Sign-extend the immediate. */
+ immed = (GET_OP (insn, IMMY) ^ 0x100) - 0x100;
+ if (immed >= -2 && immed <= 1)
+ immed ^= 0x100;
+ immed = immed << 2;
+ iprintf (is, "%d", immed);
+ break;
+
+ default:
+ /* xgettext:c-format */
+ iprintf (is,
+ _("# internal disassembler error, "
+ "unrecognized modifier (m%c)"),
+ *s);
+ abort ();
+ }
+ break;
+
+ default:
+ /* xgettext:c-format */
+ iprintf (is,
+ _("# internal disassembler error, "
+ "unrecognized modifier (%c)"),
+ *s);
+ abort ();
+ }
+ }
+
+ /* Figure out instruction type and branch delay information. */
+ if ((op->pinfo
+ & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0)
+ info->branch_delay_insns = 1;
+ if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
+ | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
+ {
+ if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0)
+ info->insn_type = dis_jsr;
+ else
+ info->insn_type = dis_branch;
+ }
+ else if (((op->pinfo & INSN_COND_BRANCH_DELAY)
+ | (op->pinfo2 & INSN2_COND_BRANCH)) != 0)
+ {
+ if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
+ info->insn_type = dis_condjsr;
+ else
+ info->insn_type = dis_condbranch;
+ }
+ else if ((op->pinfo
+ & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0)
+ info->insn_type = dis_dref;
+
+ return length;
+ }
+ }
+#undef GET_OP
+
+ iprintf (is, "0x%x", insn);
+ info->insn_type = dis_noninsn;
+
+ return length;
+}
+
+/* Return 1 if a symbol associated with the location being disassembled
+ indicates a compressed (MIPS16 or microMIPS) mode. We iterate over
+ all the symbols at the address being considered assuming if at least
+ one of them indicates code compression, then such code has been
+ genuinely produced here (other symbols could have been derived from
+ function symbols defined elsewhere or could define data). Otherwise,
+ return 0. */
+
+static bfd_boolean
+is_compressed_mode_p (struct disassemble_info *info)
+{
+ elf_symbol_type *symbol;
+ int pos;
+ int i;
+
+ for (i = 0; i < info->num_symbols; i++)
+ {
+ pos = info->symtab_pos + i;
+
+ if (bfd_asymbol_flavour (info->symtab[pos]) != bfd_target_elf_flavour)
+ continue;
+
+ symbol = (elf_symbol_type *) info->symtab[pos];
+ if ((!micromips_ase
+ && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
+ || (micromips_ase
+ && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
+ return 1;
+ }
+
+ return 0;
+}
+
/* In an environment where we do not know the symbol type of the
instruction we are forced to assume that the low order bit of the
instructions' address may mark it as a mips16 instruction. If we
@@ -2152,26 +2971,30 @@ _print_insn_mips (bfd_vma memaddr,
struct disassemble_info *info,
enum bfd_endian endianness)
{
+ int (*print_insn_compr) (bfd_vma, struct disassemble_info *);
bfd_byte buffer[INSNLEN];
int status;
set_default_mips_dis_options (info);
parse_mips_dis_options (info->disassembler_options);
+ if (info->mach == bfd_mach_mips16)
+ return print_insn_mips16 (memaddr, info);
+ if (info->mach == bfd_mach_mips_micromips)
+ return print_insn_micromips (memaddr, info);
+
+ print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips;
+
#if 1
- /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
+ /* FIXME: If odd address, this is CLEARLY a compressed instruction. */
/* Only a few tools will work this way. */
if (memaddr & 0x01)
- return print_insn_mips16 (memaddr, info);
+ return print_insn_compr (memaddr, info);
#endif
#if SYMTAB_AVAILABLE
- if (info->mach == bfd_mach_mips16
- || (info->symbols != NULL
- && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
- && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
- ->internal_elf_sym.st_other)))
- return print_insn_mips16 (memaddr, info);
+ if (is_compressed_mode_p (info))
+ return print_insn_compr (memaddr, info);
#endif
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);