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authorJan Beulich <jbeulich@suse.com>2023-03-31 08:19:58 +0200
committerJan Beulich <jbeulich@suse.com>2023-03-31 08:19:58 +0200
commitd0c2e3ec82275af986ecba93b1a8602fc9a4abbd (patch)
tree150174c45610cae8cae6df29a758b971518a48c7 /opcodes
parentedd67638687a06788c8c69c75e139bca8f94f1a3 (diff)
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x86: parse VEX and alike specifiers for .insn
All encoding spaces can be used this way; there's a certain risk that the bits presently reserved could be used for other purposes down the road, but people using .insn are expected to know what they're doing anyway. Plus this way there's at least _some_ way to have those bits set. For now this will only allow operand-less insns to be encoded this way.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/i386-opc.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index efe3383..23d93ae 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -628,12 +628,14 @@ enum
3: 256bit EVEX prefix.
4: Length-ignored (LIG) EVEX prefix.
5: Length determined from actual operands.
+ 6: L'L = 3 (reserved, .insn only)
*/
#define EVEX512 1
#define EVEX128 2
#define EVEX256 3
#define EVEXLIG 4
#define EVEXDYN 5
+#define EVEX_L3 6
EVex,
/* AVX512 masking support: