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| author | Jiajie Chen <c@jia.je> | 2023-10-26 17:35:14 +0800 |
|---|---|---|
| committer | liuzhensong <liuzhensong@loongson.cn> | 2023-11-27 15:18:15 +0800 |
| commit | cd51849c90e8fd13779bec69f5d4c7aadf03a532 (patch) | |
| tree | ec4ca36753b60f8e06e4fb5b2eb8ee48afa13abe /opcodes | |
| parent | 9ff4752d0f6d46ca0f7d275ea07e05790ac8dd1d (diff) | |
| download | gdb-cd51849c90e8fd13779bec69f5d4c7aadf03a532.zip gdb-cd51849c90e8fd13779bec69f5d4c7aadf03a532.tar.gz gdb-cd51849c90e8fd13779bec69f5d4c7aadf03a532.tar.bz2 | |
as: Add new estimated reciprocal instructions in LoongArch v1.1
New estimated reciprocal instructions in LoongArch v1.1:
- frecipe.s/d
- frsqrte.s/d
- vfrecipe.s/d
- vfrsqrte.s/d
- xvfrecipe.s/d
- xvfrsqrte.s/d
Signed-off-by: Jiajie Chen <c@jia.je>
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/loongarch-opc.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index e110735..15c7da6 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -482,6 +482,8 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] = { 0x01144400, 0xfffffc00, "fsqrt.s", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x01145400, 0xfffffc00, "frecip.s", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x01146400, 0xfffffc00, "frsqrt.s", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01147400, 0xfffffc00, "frecipe.s", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01148400, 0xfffffc00, "frsqrte.s", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x01149400, 0xfffffc00, "fmov.s", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x0114a400, 0xfffffc00, "movgr2fr.w", "f0:5,r5:5", 0, 0, 0, 0 }, { 0x0114ac00, 0xfffffc00, "movgr2frh.w", "f0:5,r5:5", 0, 0, 0, 0 }, @@ -528,6 +530,8 @@ static struct loongarch_opcode loongarch_double_float_opcodes[] = { 0x01144800, 0xfffffc00, "fsqrt.d", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x01145800, 0xfffffc00, "frecip.d", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x01146800, 0xfffffc00, "frsqrt.d", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01147800, 0xfffffc00, "frecipe.d", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01148800, 0xfffffc00, "frsqrte.d", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x01149800, 0xfffffc00, "fmov.d", "f0:5,f5:5", 0, 0, 0, 0 }, { 0x0114a800, 0xfffffc00, "movgr2fr.d", "f0:5,r5:5", 0, 0, 0, 0 }, { 0x0114b800, 0xfffffc00, "movfr2gr.d", "r0:5,f5:5", 0, 0, 0, 0 }, @@ -1424,6 +1428,10 @@ static struct loongarch_opcode loongarch_lsx_opcodes[] = { 0x729cf800, 0xfffffc00, "vfrecip.d", "v0:5,v5:5", 0, 0, 0, 0}, { 0x729d0400, 0xfffffc00, "vfrsqrt.s", "v0:5,v5:5", 0, 0, 0, 0}, { 0x729d0800, 0xfffffc00, "vfrsqrt.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d1400, 0xfffffc00, "vfrecipe.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d1800, 0xfffffc00, "vfrecipe.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d2400, 0xfffffc00, "vfrsqrte.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d2800, 0xfffffc00, "vfrsqrte.d", "v0:5,v5:5", 0, 0, 0, 0}, { 0x729d3400, 0xfffffc00, "vfrint.s", "v0:5,v5:5", 0, 0, 0, 0}, { 0x729d3800, 0xfffffc00, "vfrint.d", "v0:5,v5:5", 0, 0, 0, 0}, { 0x729d4400, 0xfffffc00, "vfrintrm.s", "v0:5,v5:5", 0, 0, 0, 0}, @@ -2169,6 +2177,10 @@ static struct loongarch_opcode loongarch_lasx_opcodes[] = { 0x769cf800, 0xfffffc00, "xvfrecip.d", "x0:5,x5:5", 0, 0, 0, 0}, { 0x769d0400, 0xfffffc00, "xvfrsqrt.s", "x0:5,x5:5", 0, 0, 0, 0}, { 0x769d0800, 0xfffffc00, "xvfrsqrt.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d1400, 0xfffffc00, "xvfrecipe.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d1800, 0xfffffc00, "xvfrecipe.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d2400, 0xfffffc00, "xvfrsqrte.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d2800, 0xfffffc00, "xvfrsqrte.d", "x0:5,x5:5", 0, 0, 0, 0}, { 0x769d3400, 0xfffffc00, "xvfrint.s", "x0:5,x5:5", 0, 0, 0, 0}, { 0x769d3800, 0xfffffc00, "xvfrint.d", "x0:5,x5:5", 0, 0, 0, 0}, { 0x769d4400, 0xfffffc00, "xvfrintrm.s", "x0:5,x5:5", 0, 0, 0, 0}, |