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authorJie Zhang <jie.zhang@analog.com>2009-09-03 16:17:36 +0000
committerJie Zhang <jie.zhang@analog.com>2009-09-03 16:17:36 +0000
commitc958a8a8fb341605fa49cb30d62e98f1b833f542 (patch)
tree4842b85e37b23a13c68aa40ccaf409f9e10cdd18 /opcodes
parent1d3ad4d0b0eafa4c7182f41077b6bfa1d8bc53c8 (diff)
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gas/
* config/bfin-defs.h (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. * config/bfin-parse.y (asm_1): Check illegal register move instructions. gas/testsuite/ * gas/bfin/expected_move_errors.s, gas/bfin/expected_move_errors.l: Add "LC1 = I0;". * gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W". opcodes/ * bfin-dis.c (IS_DREG): Define. (IS_PREG): Define. (IS_AREG): Define. (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. (decode_REGMV_0): Check illegal register move instructions.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog10
-rw-r--r--opcodes/bfin-dis.c24
2 files changed, 33 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index de8083c..0cdc676 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2009-09-03 Jie Zhang <jie.zhang@analog.com>
+
+ * bfin-dis.c (IS_DREG): Define.
+ (IS_PREG): Define.
+ (IS_AREG): Define.
+ (IS_GENREG): Define.
+ (IS_DAGREG): Define.
+ (IS_SYSREG): Define.
+ (decode_REGMV_0): Check illegal register move instructions.
+
2009-09-03 Dave Korn <dave.korn.cygwin@gmail.com>
* Makefile.am (BUILD_LIBINTL): New variable.
diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c
index 0ab6564..18887a9 100644
--- a/opcodes/bfin-dis.c
+++ b/opcodes/bfin-dis.c
@@ -432,9 +432,18 @@ static enum machine_registers decode_allregs[] =
REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
- REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_LASTREG,
+ REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
+ REG_LASTREG,
};
+#define IS_DREG(g,r) ((g) == 0)
+#define IS_PREG(g,r) ((g) == 1)
+#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
+#define IS_GENREG(g,r) ((g) == 0 || (g) == 1 || IS_AREG (g, r))
+#define IS_DAGREG(g,r) ((g) == 2 || (g) == 3)
+#define IS_SYSREG(g,r) \
+ (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
+
#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
@@ -1324,6 +1333,19 @@ decode_REGMV_0 (TIword iw0, disassemble_info *outf)
int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
+ if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src))
+ || (IS_GENREG (gd, dst) && IS_DAGREG (gs, src))
+ || (IS_DAGREG (gd, dst) && IS_GENREG (gs, src))
+ || (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src))
+ || (IS_GENREG (gd, dst) && gs == 7 && src == 0)
+ || (gd == 7 && dst == 0 && IS_GENREG (gs, src))
+ || (IS_DREG (gd, dst) && IS_SYSREG (gs, src))
+ || (IS_PREG (gd, dst) && IS_SYSREG (gs, src))
+ || (IS_SYSREG (gd, dst) && IS_DREG (gs, src))
+ || (IS_SYSREG (gd, dst) && IS_PREG (gs, src))
+ || (IS_SYSREG (gd, dst) && gs == 7 && src == 0)))
+ return 0;
+
OUTS (outf, allregs (dst, gd));
OUTS (outf, " = ");
OUTS (outf, allregs (src, gs));