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authorRichard Sandiford <rdsandiford@googlemail.com>2013-05-22 18:08:26 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2013-05-22 18:08:26 +0000
commitc77c0862b26d536f91187c34c510cee96bef1f7a (patch)
treed528508e7690c671c6dc1f6d9b6194419c0bac32 /opcodes
parent45901633da81442f00f59211280e9697737131d5 (diff)
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include/opcode/
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. opcodes/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions. gas/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB. gas/testsuite/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-full.s, gas/mips/r5900-full.d: Add tests for LQ and SQ macros. * gas/mips/r5900-vu0.s, gas/mips/r5900-vu0.d: New test. * gas/mips/mips.exp: Run it.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/mips-opc.c27
2 files changed, 24 insertions, 7 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5a868c7..94cd05d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
+
+ * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
+
2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 0c43d0a..c22156d 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -914,6 +914,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, EE },
{"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_t|RD_b, 0, MMI },
{"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI },
+{"lqc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_b|WR_C2, 0, EE },
+{"lqc2", "E,A(b)", 0, (int) M_LQC2_AB, INSN_MACRO, 0, EE },
{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 },
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55},
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
@@ -1535,6 +1537,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"sq", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, 0, MMI },
{"sq", "t,A(b)", 0, (int) M_SQ_AB, INSN_MACRO, 0, MMI },
+{"sqc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, EE },
+{"sqc2", "E,A(b)", 0, (int) M_SQC2_AB, INSN_MACRO, 0, EE },
{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2, SF },
{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
@@ -1781,16 +1785,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
-{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE },
+{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
-{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2|EE },
+{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
-{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE },
+{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
-{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2|EE },
+{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
-{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2|EE },
-{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2|EE },
+{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
+{"cfc2.i", "t,G", 0x48400001, 0xffe007ff, LCD|WR_t|RD_C2, 0, EE },
+{"cfc2.ni", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, EE },
+{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"ctc2.i", "t,G", 0x48c00001, 0xffe007ff, COD|RD_t|WR_CC, 0, EE },
+{"ctc2.ni", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, EE },
{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3, IOCT|IOCTP|IOCT2|EE },
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64, IOCT|IOCTP|IOCT2 },
@@ -1807,7 +1815,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
-
+{"qmfc2", "t,G", 0x48200000, 0xffe007ff, WR_t|RD_C2, 0, EE },
+{"qmfc2.i", "t,G", 0x48200001, 0xffe007ff, WR_t|RD_C2, 0, EE },
+{"qmfc2.ni","t,G", 0x48200000, 0xffe007ff, WR_t|RD_C2, 0, EE },
+{"qmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_t|WR_C2, 0, EE },
+{"qmtc2.i", "t,G", 0x48a00001, 0xffe007ff, RD_t|WR_C2, 0, EE },
+{"qmtc2.ni","t,G", 0x48a00000, 0xffe007ff, RD_t|WR_C2, 0, EE },
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
instructions, so they are here for the latters to take precedence. */
{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE },