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authorJan Beulich <jbeulich@suse.com>2020-07-21 14:20:11 +0200
committerJan Beulich <jbeulich@suse.com>2020-07-21 14:20:11 +0200
commitbf4ba07ca61793a1faf81c0447ba97fdc6639b50 (patch)
treefeaeb55588e260ba937d85653caaa2bb30ef759a /opcodes
parent2b42b0415aee13f1939b395c3693e679d16d0a70 (diff)
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Revert "x86: Don't display eiz with no scale"
This reverts commit 04c662e2b66bedd050f97adec19afe0fcfce9ea7. In my underlying suggestion I neglected the fact that in those cases (,%eiz,1) is the only visible indication that 32-bit addressing is in effect.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/i386-dis.c2
2 files changed, 5 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 91d7f5b..94e92b0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2020-07-21 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_E_memory): Revert previous change.
+
2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26237
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index d1d7a7d..cd8a9a8 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11818,7 +11818,7 @@ OP_E_memory (int bytemode, int sizeflag)
/* Without base nor index registers, zero-extend the
lower 32-bit displacement to 64 bits. */
disp = (unsigned int) disp;
- needindex = scale;
+ needindex = 1;
}
needaddr32 = 1;
}