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| author | Matthieu Longo <matthieu.longo@arm.com> | 2024-06-19 20:08:17 +0100 |
|---|---|---|
| committer | Matthieu Longo <matthieu.longo@arm.com> | 2024-07-05 15:39:28 +0100 |
| commit | a15809c010f32e1d72379babbd230c82e3f46901 (patch) | |
| tree | 394df32ca2738cb09b9a4b7a37a538ec8bbaf8f5 /opcodes | |
| parent | 97bf50bb61085cb516929e736b20377bd651a8c5 (diff) | |
| download | gdb-a15809c010f32e1d72379babbd230c82e3f46901.zip gdb-a15809c010f32e1d72379babbd230c82e3f46901.tar.gz gdb-a15809c010f32e1d72379babbd230c82e3f46901.tar.bz2 | |
aarch64: add E3DSE feature and its associated registers
AArch64 defines new registers for the feature e3dse (Delegated SError
exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A
feature.
This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-sys-regs.def | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 3e68035..def3dd6 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -1229,6 +1229,7 @@ SYSREG ("vbar_el2", CPENC (3,4,12,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("vbar_el3", CPENC (3,6,12,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("vdisr_el2", CPENC (3,4,12,1,1), F_ARCHEXT, AARCH64_FEATURE (RAS)) + SYSREG ("vdisr_el3", CPENC (3,6,12,1,1), F_ARCHEXT, AARCH64_FEATURE (E3DSE)) SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), 0, AARCH64_NO_FEATURES) SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), 0, AARCH64_NO_FEATURES) SYSREG ("vmpidr_el2", CPENC (3,4,0,0,5), 0, AARCH64_NO_FEATURES) @@ -1236,6 +1237,7 @@ SYSREG ("vpidr_el2", CPENC (3,4,0,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("vsctlr_el2", CPENC (3,4,2,0,0), F_ARCHEXT, AARCH64_FEATURE (V8R)) SYSREG ("vsesr_el2", CPENC (3,4,5,2,3), F_ARCHEXT, AARCH64_FEATURE (RAS)) + SYSREG ("vsesr_el3", CPENC (3,6,5,2,3), F_ARCHEXT, AARCH64_FEATURE (E3DSE)) SYSREG ("vstcr_el2", CPENC (3,4,2,6,2), F_ARCHEXT, AARCH64_FEATURE (V8_4A)) SYSREG ("vsttbr_el2", CPENC (3,4,2,6,0), F_ARCHEXT, AARCH64_FEATURES (2, V8A, V8_4A)) SYSREG ("vtcr_el2", CPENC (3,4,2,1,2), 0, AARCH64_NO_FEATURES) |