RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds fixed-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	fixed-point arithmetic instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VAADDVV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

1 files changed, 36 insertions, 0 deletions

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b0061eb..6a8d41d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2722,6 +2722,42 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vmv.v.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
 {"th.vmv.v.x",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
 {"th.vmv.v.i",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
+{"th.vsaddu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
+{"th.vsaddu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
+{"th.vsaddu.vi",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
+{"th.vsadd.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
+{"th.vsadd.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
+{"th.vsadd.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
+{"th.vssubu.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
+{"th.vssubu.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
+{"th.vssub.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
+{"th.vssub.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
+{"th.vaadd.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_TH_VAADDVV, MASK_TH_VAADDVV, match_opcode, 0 },
+{"th.vaadd.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_TH_VAADDVX, MASK_TH_VAADDVX, match_opcode, 0 },
+{"th.vaadd.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,ViVm", MATCH_TH_VAADDVI, MASK_TH_VAADDVI, match_opcode, 0 },
+{"th.vasub.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_TH_VASUBVV, MASK_TH_VASUBVV, match_opcode, 0 },
+{"th.vasub.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_TH_VASUBVX, MASK_TH_VASUBVX, match_opcode, 0 },
+{"th.vsmul.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
+{"th.vsmul.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
+{"th.vwsmaccu.vv", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VQMACCUVV, MASK_VQMACCUVV, match_opcode, 0 },
+{"th.vwsmaccu.vx", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VQMACCUVX, MASK_VQMACCUVX, match_opcode, 0 },
+{"th.vwsmacc.vv",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_VQMACCVV, MASK_VQMACCVV, match_opcode, 0 },
+{"th.vwsmacc.vx",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VQMACCVX, MASK_VQMACCVX, match_opcode, 0 },
+{"th.vwsmaccsu.vv",0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vs,VtVm", MATCH_TH_VWSMACCSUVV, MASK_TH_VWSMACCSUVV, match_opcode, 0 },
+{"th.vwsmaccsu.vx",0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_opcode, 0 },
+{"th.vwsmaccus.vx",0, INSN_CLASS_XTHEADVECTOR,  "Vd,s,VtVm", MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_opcode, 0 },
+{"th.vssrl.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
+{"th.vssrl.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
+{"th.vssrl.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
+{"th.vssra.vv",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
+{"th.vssra.vx",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
+{"th.vssra.vi",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
+{"th.vnclipu.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_opcode, 0 },
+{"th.vnclipu.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_opcode, 0 },
+{"th.vnclipu.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_opcode, 0 },
+{"th.vnclip.vv",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_opcode, 0 },
+{"th.vnclip.vx",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 },
+{"th.vnclip.vi",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 },
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },