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| author | Jim Wilson <jimw@sifive.com> | 2019-07-05 15:19:11 +0800 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2019-07-05 15:19:11 +0800 |
| commit | 98602811d838077269e361e9d807fe530c780011 (patch) | |
| tree | adddb9536e0ae27b31da8d1ae46e64fab62cda67 /opcodes | |
| parent | a0b6cbf69db7427cfdf054092062fcf82eef9a58 (diff) | |
| download | gdb-98602811d838077269e361e9d807fe530c780011.zip gdb-98602811d838077269e361e9d807fe530c780011.tar.gz gdb-98602811d838077269e361e9d807fe530c780011.tar.bz2 | |
Kito's 5-part patch set to improve .insn support.
From Kito Cheng <kito.cheng@sifive.com>
gas/ChangeLog
* doc/c-riscv.texi (Instruction Formats): Add r4 type.
* testsuite/gas/riscv/insn.d: Add testcase for r4 type.
* testsuite/gas/riscv/insn.s: Ditto.
* doc/c-riscv.texi (Instruction Formats): Add b and j type.
* testsuite/gas/riscv/insn.d: Add test case for b and j type.
* testsuite/gas/riscv/insn.s: Ditto.
* testsuite/gas/riscv/insn.s: Correct instruction type for load
and store.
* testsuite/gas/riscv/insn.d: Using regular expression to match
address.
* doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB
type and fix typo.
opcode/ChangeLog
* riscv-opc.c (riscv_insn_types): Add r4 type.
* riscv-opc.c (riscv_insn_types): Add b and j type.
* opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
format for sb type and correct s type.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 30 |
2 files changed, 35 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 882ab3f..85a2842 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +2019-07-05 Kito Cheng <kito.cheng@sifive.com> + + * riscv-opc.c (riscv_insn_types): Add r4 type. + + * riscv-opc.c (riscv_insn_types): Add b and j type. + + * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect + format for sb type and correct s type. + 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index bd65259..113d1a5 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -812,6 +812,23 @@ const struct riscv_opcode riscv_insn_types[] = {"r", 0, {"I", 0}, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 }, {"r", 0, {"I", 0}, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 }, +{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 }, + {"i", 0, {"I", 0}, "O4,F3,d,s,j", 0, 0, match_opcode, 0 }, {"i", 0, {"I", 0}, "O4,F3,D,s,j", 0, 0, match_opcode, 0 }, {"i", 0, {"I", 0}, "O4,F3,d,S,j", 0, 0, match_opcode, 0 }, @@ -820,16 +837,18 @@ const struct riscv_opcode riscv_insn_types[] = {"i", 0, {"I", 0}, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 }, {"i", 0, {"I", 0}, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 }, -{"s", 0, {"I", 0}, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 }, -{"s", 0, {"I", 0}, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 }, +{"s", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 }, +{"s", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 }, {"sb", 0, {"I", 0}, "O4,F3,s,t,p", 0, 0, match_opcode, 0 }, {"sb", 0, {"I", 0}, "O4,F3,S,t,p", 0, 0, match_opcode, 0 }, {"sb", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 }, {"sb", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 }, -{"sb", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 }, -{"sb", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 }, +{"b", 0, {"I", 0}, "O4,F3,s,t,p", 0, 0, match_opcode, 0 }, +{"b", 0, {"I", 0}, "O4,F3,S,t,p", 0, 0, match_opcode, 0 }, +{"b", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 }, +{"b", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 }, {"u", 0, {"I", 0}, "O4,d,u", 0, 0, match_opcode, 0 }, {"u", 0, {"I", 0}, "O4,D,u", 0, 0, match_opcode, 0 }, @@ -837,6 +856,9 @@ const struct riscv_opcode riscv_insn_types[] = {"uj", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 }, {"uj", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 }, +{"j", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 }, +{"j", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 }, + {"cr", 0, {"C", 0}, "O2,CF4,d,CV", 0, 0, match_opcode, 0 }, {"cr", 0, {"C", 0}, "O2,CF4,D,CV", 0, 0, match_opcode, 0 }, {"cr", 0, {"C", 0}, "O2,CF4,d,CT", 0, 0, match_opcode, 0 }, |