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| author | Catherine Moore <clm@redhat.com> | 2008-11-18 15:45:05 +0000 |
|---|---|---|
| committer | Catherine Moore <clm@redhat.com> | 2008-11-18 15:45:05 +0000 |
| commit | 8e79c3df515af53e2f21aed2d8ad7226af33f447 (patch) | |
| tree | d2d0bcdd9e2019944eaf2edf8b5090f3368bc041 /opcodes | |
| parent | dc80fd5cfc9fbf3a658a90c67edd321e7a40bf0b (diff) | |
| download | gdb-8e79c3df515af53e2f21aed2d8ad7226af33f447.zip gdb-8e79c3df515af53e2f21aed2d8ad7226af33f447.tar.gz gdb-8e79c3df515af53e2f21aed2d8ad7226af33f447.tar.bz2 | |
Add support for ARM half-precision conversion instructions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 7 |
2 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ee6bd10..2d8f214 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2008-11-18 Catherine Moore <clm@codesourcery.com> + + * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt + instructions. + (neon_opcodes): Likewise. + (print_insn_coprocessor): Print 't' or 'b' for vcvt + instructions. + 2008-11-14 Tristan Gingold <gingold@adacore.com> * makefile.vms (OBJS): Update list of objects. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 155e495..1be7bbc 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -264,6 +264,9 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, + /* Half-precision conversion instructions. */ + {FPU_NEON_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, + {FPU_NEON_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, /* Floating point coprocessor (VFP) instructions */ {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"}, @@ -504,6 +507,10 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, + /* Half-precision conversions. */ + {FPU_NEON_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, + {FPU_NEON_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, + /* Two registers, miscellaneous */ {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, |