MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a

The MMI instruction set has been implemented in many Loongson
processors.  There is a lot of software optimized for MMI.  This patch
splits MMI from loongson2f/3a, and adds GAS and disassembler options for
MMI instructions.

2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
            Maciej W. Rozycki  <macro@mips.com>

bfd/
	* elfxx-mips.c (print_mips_ases): Add MMI extension.

binutils/
	* readelf.c (print_mips_ases): Add MMI extension.

gas/
	* NEWS: Mention MultiMedia extensions Instructions (MMI)
	support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and
	OPTION_NO_LOONGSON_MMI.
	(md_longopts): Likewise.
	(mips_ases): Define availability for MMI.
	(mips_convert_ase_flags): Map ASE_LOONGSON_MMI to
	AFL_ASE_LOONGSON_MMI.
	(mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a.
	(md_show_usage): Add help for -mloongson-mmi and
	-mno-loongson-mmi.
	* doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi.
	* doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi,
	.set loongson-mmi and .set noloongson-mmi.
	* testsuite/gas/mips/loongson-2f.d: Move mmi test to ...
	* testsuite/gas/mips/loongson-2f-mmi.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-2f.s: Move mmi test to ...
	* testsuite/gas/mips/loongson-2f-mmi.s: Here.
	* testsuite/gas/mips/loongson-3a.d: Move mmi test to ...
	* testsuite/gas/mips/loongson-3a-mmi.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-3a.s: Move mmi test to ...
	* testsuite/gas/mips/loongson-3a-mmi.s: Here.
	* testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and
	loongson-3a-mmi tests.

include/
	* elf/mips.h (AFL_ASE_MMI): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
	* opcode/mips.h (ASE_LOONGSON_MMI): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
	loongson3a descriptors.
	(parse_mips_ase_option): Handle -M loongson-mmi option.
	(print_mips_disassembler_options): Document -M loongson-mmi.
	* mips-opc.c (LMMI): New macro.
	(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
	instructions.

3 files changed, 106 insertions, 82 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5e71f75..076af1f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
+	    Maciej W. Rozycki  <macro@mips.com>
+
+	* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
+	loongson3a descriptors.
+	(parse_mips_ase_option): Handle -M loongson-mmi option.
+	(print_mips_disassembler_options): Document -M loongson-mmi.
+	* mips-opc.c (LMMI): New macro.
+	(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
+	instructions.
+
 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index bbf2132..4663016 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -626,11 +626,11 @@ const struct mips_arch_choice mips_arch_choices[] =
     NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "loongson2f",   1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
-    ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
+    ISA_MIPS3 | INSN_LOONGSON_2F, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
     NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "loongson3a",   1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
-    ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
+    ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
     NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
 
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
@@ -935,6 +935,12 @@ parse_mips_ase_option (const char *option)
       return TRUE;
     }
 
+  if (CONST_STRNEQ (option, "loongson-mmi"))
+    {
+      mips_ase |= ASE_LOONGSON_MMI;
+      return TRUE;
+    }
+
   return FALSE;
 }
 
@@ -2582,6 +2588,10 @@ static struct
   { "ginv",       N_("Recognize the Global INValidate (GINV) ASE "
 		     "instructions.\n"),
 		  MIPS_OPTION_ARG_NONE },
+  { "loongson-mmi",
+		  N_("Recognize the Loongson MultiMedia extensions "
+		     "Instructions (MMI) ASE instructions.\n"),
+		  MIPS_OPTION_ARG_NONE },
   { "gpr-names=", N_("Print GPR names according to specified ABI.\n\
                   Default: based on binary being disassembled.\n"),
 		  MIPS_OPTION_ARG_ABI },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 1cbcbc6..31532f8 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -412,6 +412,9 @@ decode_mips_operand (const char *p)
 /* Global INValidate (GINV) support.  */
 #define GINV	ASE_GINV
 
+/* Loongson MultiMedia extensions Instructions (MMI) support.  */
+#define LMMI	ASE_LOONGSON_MMI
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -652,7 +655,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"add",			"d,v,t",	0x00000020, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"add",			"t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"add",			"D,S,T",	0x45c00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
-{"add",			"D,S,T",	0x4b40000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F|IL3A,	0,	0 },
+{"add",			"D,S,T",	0x4b40000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		0,		LMMI,	0 },
 {"add.s",		"D,V,T",	0x46000000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I1,		0,	0 },
 {"add.d",		"D,V,T",	0x46200000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I1,		0,	SF },
 {"add.ob",		"X,Y,Q",	0x7800000b, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
@@ -673,7 +676,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addu",		"d,v,t",	0x00000021, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"addu",		"t,r,I",	0,    (int) M_ADDU_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"addu",		"D,S,T",	0x45800000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
-{"addu",		"D,S,T",	0x4b00000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F|IL3A,	0,	0 },
+{"addu",		"D,S,T",	0x4b00000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		0,		LMMI,	0 },
 {"alni.ob",		"X,Y,Z,O",	0x78000018, 0xff00003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"alni.ob",		"D,S,T,%",	0x48000018, 0xff00003f,	WR_1|RD_2|RD_3|FP_D, 	0,		N54,		0,	0 },
 {"alni.qh",		"X,Y,Z,O",	0x7800001a, 0xff00003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
@@ -683,7 +686,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"and",			"d,v,t",	0x00000024, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"and",			"t,r,I",	0,    (int) M_AND_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"and",			"D,S,T",	0x47c00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"and",			"D,S,T",	0x4bc00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"and",			"D,S,T",	0x4bc00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"and.ob",		"X,Y,Q",	0x7800000c, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"and.ob",		"D,S,Q",	0x4800000c, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"and.qh",		"X,Y,Q",	0x7820000c, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
@@ -1001,7 +1004,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dadd",		"d,v,t",	0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
 {"dadd",		"t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		0,		I3,		0,	I69 },
 {"dadd",		"D,S,T",	0x45e00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"dadd",		"D,S,T",	0x4b60000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"dadd",		"D,S,T",	0x4b60000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"daddi",		"t,r,j",	0x60000000, 0xfc000000, WR_1|RD_2,		0,		I3,		0,	I69 },
 {"daddiu",		"t,r,j",	0x64000000, 0xfc000000, WR_1|RD_2,		0,		I3,		0,	0 },
 {"daddu",		"d,v,t",	0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
@@ -1141,25 +1144,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsll",		"d,w,>",	0x0000003c, 0xffe0003f, WR_1|RD_2,		0,		I3,		0,	0 }, /* dsll32 */
 {"dsll",		"d,w,<",	0x00000038, 0xffe0003f,	WR_1|RD_2,		0,		I3,		0,	0 },
 {"dsll",		"D,S,T",	0x45a00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"dsll",		"D,S,T",	0x4b20000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"dsll",		"D,S,T",	0x4b20000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"dsrav",		"d,t,s",	0x00000017, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
 {"dsra32",		"d,w,<",	0x0000003f, 0xffe0003f, WR_1|RD_2,		0,		I3,		0,	0 },
 {"dsra",		"d,w,s",	0x00000017, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I3,		0,	0 }, /* dsrav */
 {"dsra",		"d,w,>",	0x0000003f, 0xffe0003f, WR_1|RD_2,		0,		I3,		0,	0 }, /* dsra32 */
 {"dsra",		"d,w,<",	0x0000003b, 0xffe0003f,	WR_1|RD_2,		0,		I3,		0,	0 },
 {"dsra",		"D,S,T",	0x45e00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"dsra",		"D,S,T",	0x4b60000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"dsra",		"D,S,T",	0x4b60000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"dsrlv",		"d,t,s",	0x00000016, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
 {"dsrl32",		"d,w,<",	0x0000003e, 0xffe0003f, WR_1|RD_2,		0,		I3,		0,	0 },
 {"dsrl",		"d,w,s",	0x00000016, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I3,		0,	0 }, /* dsrlv */
 {"dsrl",		"d,w,>",	0x0000003e, 0xffe0003f, WR_1|RD_2,		0,		I3,		0,	0 }, /* dsrl32 */
 {"dsrl",		"d,w,<",	0x0000003a, 0xffe0003f,	WR_1|RD_2,		0,		I3,		0,	0 },
 {"dsrl",		"D,S,T",	0x45a00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"dsrl",		"D,S,T",	0x4b20000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"dsrl",		"D,S,T",	0x4b20000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"dsub",		"d,v,t",	0x0000002e, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
 {"dsub",		"d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,		0,		I3,		0,	I69 },
 {"dsub",		"D,S,T",	0x45e00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"dsub",		"D,S,T",	0x4b60000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"dsub",		"D,S,T",	0x4b60000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"dsubu",		"d,v,t",	0x0000002f, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
 {"dsubu",		"d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,		0,		I3,		0,	0 },
 {"dvpe",		"",		0x41600001, 0xffffffff, TRAP,			0,		0,		MT32,	0 },
@@ -1628,7 +1631,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nor",			"d,v,t",	0x00000027, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"nor",			"t,r,I",	0,    (int) M_NOR_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"nor",			"D,S,T",	0x47a00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"nor",			"D,S,T",	0x4ba00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"nor",			"D,S,T",	0x4ba00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"nor.ob",		"X,Y,Q",	0x7800000f, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"nor.ob",		"D,S,Q",	0x4800000f, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"nor.qh",		"X,Y,Q",	0x7820000f, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
@@ -1636,7 +1639,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"or",			"d,v,t",	0x00000025, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"or",			"t,r,I",	0,    (int) M_OR_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"or",			"D,S,T",	0x45a00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"or",			"D,S,T",	0x4b20000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"or",			"D,S,T",	0x4b20000c, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"or.ob",		"X,Y,Q",	0x7800000e, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"or.ob",		"D,S,Q",	0x4800000e, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"or.qh",		"X,Y,Q",	0x7820000e, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
@@ -1849,7 +1852,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"seq",			"d,v,t",	0,    (int) M_SEQ,	INSN_MACRO,		0,		I1,		0,	0 },
 {"seq",			"d,v,I",	0,    (int) M_SEQ_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"seq",			"S,T",		0x46a00032, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"seq",			"S,T",		0x4ba0000c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"seq",			"S,T",		0x4ba0000c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		0,		LMMI,	0 },
 {"seqi",		"t,r,+Q",	0x7000002e, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
 {"sge",			"d,v,t",	0,    (int) M_SGE,	INSN_MACRO,		0,		I1,		0,	0 },
 {"sge",			"d,v,I",	0,    (int) M_SGE_I,	INSN_MACRO,		0,		I1,		0,	0 },
@@ -1879,29 +1882,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sle",			"d,v,t",	0,    (int) M_SLE,	INSN_MACRO,		0,		I1,		0,	0 },
 {"sle",			"d,v,I",	0,    (int) M_SLE_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"sle",			"S,T",		0x46a0003e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"sle",			"S,T",		0x4ba0000e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"sle",			"S,T",		0x4ba0000e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		0,		LMMI,	0 },
 {"sleu",		"d,v,t",	0,    (int) M_SLEU,	INSN_MACRO,		0,		I1,		0,	0 },
 {"sleu",		"d,v,I",	0,    (int) M_SLEU_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"sleu",		"S,T",		0x4680003e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"sleu",		"S,T",		0x4b80000e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"sleu",		"S,T",		0x4b80000e, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		0,		LMMI,	0 },
 {"sllv",		"d,t,s",	0x00000004, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"sll",			"d,w,s",	0x00000004, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 }, /* sllv */
 {"sll",			"d,w,<",	0x00000000, 0xffe0003f,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"sll",			"D,S,T",	0x45800002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"sll",			"D,S,T",	0x4b00000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"sll",			"D,S,T",	0x4b00000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"sll.ob",		"X,Y,Q",	0x78000010, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"sll.ob",		"D,S,Q",	0x48000010, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"sll.qh",		"X,Y,Q",	0x78200010, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
 {"slt",			"d,v,t",	0x0000002a, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"slt",			"d,v,I",	0,    (int) M_SLT_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"slt",			"S,T",		0x46a0003c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"slt",			"S,T",		0x4ba0000d, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"slt",			"S,T",		0x4ba0000d, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		0,		LMMI,	0 },
 {"slti",		"t,r,j",	0x28000000, 0xfc000000,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"sltiu",		"t,r,j",	0x2c000000, 0xfc000000,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"sltu",		"d,v,t",	0x0000002b, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"sltu",		"d,v,I",	0,    (int) M_SLTU_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"sltu",		"S,T",		0x4680003c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"sltu",		"S,T",		0x4b80000d, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"sltu",		"S,T",		0x4b80000d, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		0,		LMMI,	0 },
 {"sne",			"d,v,t",	0x7000002b, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		IOCT,		0,	0 },
 {"sne",			"d,v,t",	0,    (int) M_SNE,	INSN_MACRO,		0,		I1,		0,	0 },
 {"sne",			"d,v,I",	0,    (int) M_SNE_I,	INSN_MACRO,		0,		I1,		0,	0 },
@@ -1917,13 +1920,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sra",			"d,w,s",	0x00000007, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 }, /* srav */
 {"sra",			"d,w,<",	0x00000003, 0xffe0003f,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"sra",			"D,S,T",	0x45c00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"sra",			"D,S,T",	0x4b40000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"sra",			"D,S,T",	0x4b40000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"sra.qh",		"X,Y,Q",	0x78200013, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
 {"srlv",		"d,t,s",	0x00000006, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"srl",			"d,w,s",	0x00000006, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 }, /* srlv */
 {"srl",			"d,w,<",	0x00000002, 0xffe0003f,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"srl",			"D,S,T",	0x45800003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"srl",			"D,S,T",	0x4b00000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"srl",			"D,S,T",	0x4b00000f, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"srl.ob",		"X,Y,Q",	0x78000012, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"srl.ob",		"D,S,Q",	0x48000012, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"srl.qh",		"X,Y,Q",	0x78200012, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
@@ -1932,7 +1935,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sub",			"d,v,t",	0x00000022, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"sub",			"d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		0,		I1,		0,	I37 },
 {"sub",			"D,S,T",	0x45c00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
-{"sub",			"D,S,T",	0x4b40000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F|IL3A,	0,	0 },
+{"sub",			"D,S,T",	0x4b40000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		0,		LMMI,	0 },
 {"sub.d",		"D,V,T",	0x46200001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		I1,		0,	SF },
 {"sub.s",		"D,V,T",	0x46000001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I1,		0,	0 },
 {"sub.ob",		"X,Y,Q",	0x7800000a, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
@@ -1948,7 +1951,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"subu",		"d,v,t",	0x00000023, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"subu",		"d,v,I",	0,    (int) M_SUBU_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"subu",		"D,S,T",	0x45800001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2E,		0,	0 },
-{"subu",		"D,S,T",	0x4b00000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		IL2F|IL3A,	0,	0 },
+{"subu",		"D,S,T",	0x4b00000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		0,		LMMI,	0 },
 {"suspend",		"",		0x42000022, 0xffffffff,	0,			0,		V1,		0,	0 },
 {"suxc1",		"S,t(b)",	0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D,	0,		I5_33|N55,	0,	I37},
 {"sw",			"t,o(b)",	0xac000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I1,		0,	0 },
@@ -2069,7 +2072,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",			"d,v,t",	0x00000026, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"xor",			"t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"xor",			"D,S,T",	0x47800002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"xor",			"D,S,T",	0x4b800002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"xor",			"D,S,T",	0x4b800002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"xor.ob",		"X,Y,Q",	0x7800000d, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"xor.ob",		"D,S,Q",	0x4800000d, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"xor.qh",		"X,Y,Q",	0x7820000d, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
@@ -2470,139 +2473,139 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmodu.g",		"d,s,t",	0x7000001f, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		IL2F,		0,	0 },
 {"gsdmodu",		"d,s,t",	0x7000001f, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		IL3A,		0,	0 },
 {"packsshb",		"D,S,T",	0x47400002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"packsshb",		"D,S,T",	0x4b400002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"packsshb",		"D,S,T",	0x4b400002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"packsswh",		"D,S,T",	0x47200002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"packsswh",		"D,S,T",	0x4b200002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"packsswh",		"D,S,T",	0x4b200002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"packushb",		"D,S,T",	0x47600002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"packushb",		"D,S,T",	0x4b600002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"packushb",		"D,S,T",	0x4b600002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"paddb",		"D,S,T",	0x47c00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"paddb",		"D,S,T",	0x4bc00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"paddb",		"D,S,T",	0x4bc00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"paddb",		"d,s,t",	0x70000208, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"paddh",		"D,S,T",	0x47400000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"paddh",		"d,s,t",	0x70000108, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
-{"paddh",		"D,S,T",	0x4b400000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"paddh",		"D,S,T",	0x4b400000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"paddw",		"D,S,T",	0x47600000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"paddw",		"D,S,T",	0x4b600000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"paddw",		"D,S,T",	0x4b600000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"paddw",		"d,s,t",	0x70000008, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"paddd",		"D,S,T",	0x47e00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"paddd",		"D,S,T",	0x4be00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"paddd",		"D,S,T",	0x4be00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"paddsb",		"D,S,T",	0x47800000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"paddsb",		"D,S,T",	0x4b800000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"paddsb",		"D,S,T",	0x4b800000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"paddsb",		"d,s,t",	0x70000608, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"paddsh",		"D,S,T",	0x47000000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"paddsh",		"D,S,T",	0x4b000000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"paddsh",		"D,S,T",	0x4b000000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"paddsh",		"d,s,t",	0x70000508, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"paddusb",		"D,S,T",	0x47a00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"paddusb",		"D,S,T",	0x4ba00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"paddusb",		"D,S,T",	0x4ba00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"paddush",		"D,S,T",	0x47200000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"paddush",		"D,S,T",	0x4b200000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"paddush",		"D,S,T",	0x4b200000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pandn",		"D,S,T",	0x47e00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pandn",		"D,S,T",	0x4be00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pandn",		"D,S,T",	0x4be00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pavgb",		"D,S,T",	0x46600000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pavgb",		"D,S,T",	0x4b200008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pavgb",		"D,S,T",	0x4b200008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pavgh",		"D,S,T",	0x46400000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pavgh",		"D,S,T",	0x4b000008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pavgh",		"D,S,T",	0x4b000008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pcmpeqb",		"D,S,T",	0x46c00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pcmpeqb",		"D,S,T",	0x4b800009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pcmpeqb",		"D,S,T",	0x4b800009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pcmpeqh",		"D,S,T",	0x46800001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pcmpeqh",		"D,S,T",	0x4b400009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pcmpeqh",		"D,S,T",	0x4b400009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pcmpeqw",		"D,S,T",	0x46400001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pcmpeqw",		"D,S,T",	0x4b000009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pcmpeqw",		"D,S,T",	0x4b000009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pcmpgtb",		"D,S,T",	0x46e00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pcmpgtb",		"D,S,T",	0x4ba00009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pcmpgtb",		"D,S,T",	0x4ba00009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pcmpgth",		"D,S,T",	0x46a00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pcmpgth",		"D,S,T",	0x4b600009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pcmpgth",		"D,S,T",	0x4b600009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pcmpgtw",		"D,S,T",	0x46600001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pcmpgtw",		"D,S,T",	0x4b200009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pcmpgtw",		"D,S,T",	0x4b200009, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pextrh",		"D,S,T",	0x45c00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pextrh",		"D,S,T",	0x4b40000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pextrh",		"D,S,T",	0x4b40000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pinsrh_0",		"D,S,T",	0x47800003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pinsrh_0",		"D,S,T",	0x4b800003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pinsrh_0",		"D,S,T",	0x4b800003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pinsrh_1",		"D,S,T",	0x47a00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pinsrh_1",		"D,S,T",	0x4ba00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pinsrh_1",		"D,S,T",	0x4ba00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pinsrh_2",		"D,S,T",	0x47c00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pinsrh_2",		"D,S,T",	0x4bc00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pinsrh_2",		"D,S,T",	0x4bc00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pinsrh_3",		"D,S,T",	0x47e00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pinsrh_3",		"D,S,T",	0x4be00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pinsrh_3",		"D,S,T",	0x4be00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pmaddhw",		"D,S,T",	0x45e00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pmaddhw",		"D,S,T",	0x4b60000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pmaddhw",		"D,S,T",	0x4b60000e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pmaxsh",		"D,S,T",	0x46800000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pmaxsh",		"D,S,T",	0x4b400008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pmaxsh",		"D,S,T",	0x4b400008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pmaxub",		"D,S,T",	0x46c00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pmaxub",		"D,S,T",	0x4b800008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pmaxub",		"D,S,T",	0x4b800008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pminsh",		"D,S,T",	0x46a00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pminsh",		"D,S,T",	0x4b600008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pminsh",		"D,S,T",	0x4b600008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pminub",		"D,S,T",	0x46e00000, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pminub",		"D,S,T",	0x4ba00008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pminub",		"D,S,T",	0x4ba00008, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pmovmskb",		"D,S",		0x46a00005, 0xffff003f,	WR_1|RD_2|FP_D,		0,		IL2E,		0,	0 },
-{"pmovmskb",		"D,S",		0x4ba0000f, 0xffff003f,	WR_1|RD_2|FP_D,		0,		IL2F|IL3A,	0,	0 },
+{"pmovmskb",		"D,S",		0x4ba0000f, 0xffff003f,	WR_1|RD_2|FP_D,		0,		0,		LMMI,	0 },
 {"pmulhuh",		"D,S,T",	0x46e00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pmulhuh",		"D,S,T",	0x4ba0000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pmulhuh",		"D,S,T",	0x4ba0000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pmulhh",		"D,S,T",	0x46a00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pmulhh",		"D,S,T",	0x4b60000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pmulhh",		"D,S,T",	0x4b60000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pmullh",		"D,S,T",	0x46800002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pmullh",		"D,S,T",	0x4b40000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pmullh",		"D,S,T",	0x4b40000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pmuluw",		"D,S,T",	0x46c00002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pmuluw",		"D,S,T",	0x4b80000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pmuluw",		"D,S,T",	0x4b80000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"pasubub",		"D,S,T",	0x45a00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pasubub",		"D,S,T",	0x4b20000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pasubub",		"D,S,T",	0x4b20000d, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"biadd",		"D,S",		0x46800005, 0xffff003f,	WR_1|RD_2|FP_D,		0,		IL2E,		0,	0 },
-{"biadd",		"D,S",		0x4b80000f, 0xffff003f,	WR_1|RD_2|FP_D,		0,		IL2F|IL3A,	0,	0 },
+{"biadd",		"D,S",		0x4b80000f, 0xffff003f,	WR_1|RD_2|FP_D,		0,		0,		LMMI,	0 },
 {"pshufh",		"D,S,T",	0x47000002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"pshufh",		"D,S,T",	0x4b000002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"pshufh",		"D,S,T",	0x4b000002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psllh",		"D,S,T",	0x46600002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psllh",		"D,S,T",	0x4b20000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psllh",		"D,S,T",	0x4b20000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psllh",		"d,t,<",	0x70000034, 0xffe0003f,	WR_1|RD_2,		0,		MMI,		0,	0 },
 {"psllw",		"D,S,T",	0x46400002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psllw",		"D,S,T",	0x4b00000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psllw",		"D,S,T",	0x4b00000a, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psllw",		"d,t,<",	0x7000003c, 0xffe0003f,	WR_1|RD_2,		0,		MMI,		0,	0 },
 {"psrah",		"D,S,T",	0x46a00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psrah",		"D,S,T",	0x4b60000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psrah",		"D,S,T",	0x4b60000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psrah",		"d,t,<",	0x70000037, 0xffe0003f,	WR_1|RD_2,		0,		MMI,		0,	0 },
 {"psraw",		"D,S,T",	0x46800003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psraw",		"D,S,T",	0x4b40000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psraw",		"D,S,T",	0x4b40000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psraw",		"d,t,<",	0x7000003f, 0xffe0003f,	WR_1|RD_2,		0,		MMI,		0,	0 },
 {"psrlh",		"D,S,T",	0x46600003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psrlh",		"D,S,T",	0x4b20000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psrlh",		"D,S,T",	0x4b20000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psrlh",		"d,t,<",	0x70000036, 0xffe0003f,	WR_1|RD_2,		0,		MMI,		0,	0 },
 {"psrlw",		"D,S,T",	0x46400003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psrlw",		"D,S,T",	0x4b00000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psrlw",		"D,S,T",	0x4b00000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psrlw",		"d,t,<",	0x7000003e, 0xffe0003f,	WR_1|RD_2,		0,		MMI,		0,	0 },
 {"psubb",		"D,S,T",	0x47c00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psubb",		"D,S,T",	0x4bc00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psubb",		"D,S,T",	0x4bc00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psubb",		"d,s,t",	0x70000248, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"psubh",		"D,S,T",	0x47400001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psubh",		"D,S,T",	0x4b400001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psubh",		"D,S,T",	0x4b400001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psubh",		"d,s,t",	0x70000148, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"psubw",		"D,S,T",	0x47600001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psubw",		"D,S,T",	0x4b600001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psubw",		"D,S,T",	0x4b600001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psubw",		"d,s,t",	0x70000048, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"psubd",		"D,S,T",	0x47e00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psubd",		"D,S,T",	0x4be00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psubd",		"D,S,T",	0x4be00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psubsb",		"D,S,T",	0x47800001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psubsb",		"D,S,T",	0x4b800001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psubsb",		"D,S,T",	0x4b800001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psubsb",		"d,s,t",	0x70000648, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"psubsh",		"D,S,T",	0x47000001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psubsh",		"D,S,T",	0x4b000001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psubsh",		"D,S,T",	0x4b000001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psubsh",		"d,s,t",	0x70000548, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		MMI,		0,	0 },
 {"psubusb",		"D,S,T",	0x47a00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psubusb",		"D,S,T",	0x4ba00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psubusb",		"D,S,T",	0x4ba00001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"psubush",		"D,S,T",	0x47200001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"psubush",		"D,S,T",	0x4b200001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"psubush",		"D,S,T",	0x4b200001, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"punpckhbh",		"D,S,T",	0x47600003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"punpckhbh",		"D,S,T",	0x4b600003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"punpckhbh",		"D,S,T",	0x4b600003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"punpckhhw",		"D,S,T",	0x47200003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"punpckhhw",		"D,S,T",	0x4b200003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"punpckhhw",		"D,S,T",	0x4b200003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"punpckhwd",		"D,S,T",	0x46e00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"punpckhwd",		"D,S,T",	0x4ba0000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"punpckhwd",		"D,S,T",	0x4ba0000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"punpcklbh",		"D,S,T",	0x47400003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"punpcklbh",		"D,S,T",	0x4b400003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"punpcklbh",		"D,S,T",	0x4b400003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"punpcklhw",		"D,S,T",	0x47000003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"punpcklhw",		"D,S,T",	0x4b000003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"punpcklhw",		"D,S,T",	0x4b000003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"punpcklwd",		"D,S,T",	0x46c00003, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
-{"punpcklwd",		"D,S,T",	0x4b80000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"punpcklwd",		"D,S,T",	0x4b80000b, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		LMMI,	0 },
 {"sequ",		"S,T",		0x46800032, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2E,		0,	0 },
-{"sequ",		"S,T",		0x4b80000c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		IL2F|IL3A,	0,	0 },
+{"sequ",		"S,T",		0x4b80000c, 0xffe007ff,	RD_1|RD_2|WR_CC|FP_D,	0,		0,		LMMI,	0 },
 /* MIPS Enhanced VA Scheme */
 {"lbue",		"t,+j(b)",	0x7c000028, 0xfc00007f, WR_1|RD_3|LM,		0,		0,		EVA,	0 },
 {"lbue",		"t,A(b)",	0,    (int) M_LBUE_AB,	INSN_MACRO,		0,		0,		EVA,	0 },