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| author | Tamar Christina <tamar.christina@arm.com> | 2018-10-03 18:27:52 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2018-10-03 18:33:33 +0100 |
| commit | 7e84b55d8f973b011f55f604a76c2d1d989d0b6b (patch) | |
| tree | 1d860bb0c911056c9fed87fc0b3e46ec30723c91 /opcodes | |
| parent | eae424aef0b14e1765602088ac866b95d14d4a22 (diff) | |
| download | gdb-7e84b55d8f973b011f55f604a76c2d1d989d0b6b.zip gdb-7e84b55d8f973b011f55f604a76c2d1d989d0b6b.tar.gz gdb-7e84b55d8f973b011f55f604a76c2d1d989d0b6b.tar.bz2 | |
AArch64: Wire through instr_sequence
This patch introduces aarch64_instr_sequence which is a structure similar to IT
blocks on Arm in order to track instructions that introduce a constraint or
dependency on instruction 1..N positions away from the instruction that opened
the block.
The struct is also wired through to the locations that require it.
gas/
* config/tc-aarch64.c (now_instr_sequence):
(*insn_sequence, now_instr_sequence): New.
(output_operand_error_record, do_encode): Add insn_sequence.
(md_assemble): Update insn_sequence.
(try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn):
Pass insn_sequence.
* config/tc-aarch64.h (struct aarch64_segment_info_type):
Add insn_sequence.
include/
* opcode/aarch64.h (struct aarch64_instr_sequence): New.
(aarch64_opcode_encode): Use it.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
* aarch64-dis.c (insn_sequence): New.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.c | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 3 |
3 files changed, 10 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4014e2b..2ccfe8e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2018-10-03 Tamar Christina <tamar.christina@arm.com> + * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence. + * aarch64-dis.c (insn_sequence): New. + +2018-10-03 Tamar Christina <tamar.christina@arm.com> + * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN, _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN, diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 06d428b..35704cd 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1948,7 +1948,8 @@ bfd_boolean aarch64_opcode_encode (const aarch64_opcode *opcode, const aarch64_inst *inst_ori, aarch64_insn *code, aarch64_opnd_qualifier_t *qlf_seq, - aarch64_operand_error *mismatch_detail) + aarch64_operand_error *mismatch_detail, + aarch64_instr_sequence* insn_sequence ATTRIBUTE_UNUSED) { int i; const aarch64_opcode *aliased; diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index f7092b06..599727e 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -49,6 +49,9 @@ static int no_aliases = 0; /* If set disassemble as most general inst. */ static int no_notes = 1; /* If set do not print disassemble notes in the output as comments. */ +/* Currently active instruction sequence. */ +static aarch64_instr_sequence insn_sequence ATTRIBUTE_UNUSED; + static void set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED) { |