MIPS/GAS: Implement microMIPS branch/jump compaction

Convert microMIPS branches and jumps whose delay slot would be filled by
a generated NOP instruction to the corresponding compact form where one
exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap.

Do so even where the transformation switches from a 16-bit to a 32-bit
branch encoding for no benefit in code size reduction, as this is still
advantageous.  This is because a branch/NOP pair takes 2 pipeline slots
or a 2-cycle completion latency except in superscalar implementations.
Whereas a compact branch may or may not stall on its target fetch, so it
will at most have a 2-cycle completion latency and may have only 1 even
in scalar implementations, and in superscalar implementations it is
expected to have no worse latency as a branch/NOP pair has.  Also it
won't stall and therefore take the extra latency cycle in the not-taken
case.

Technically this is the same as MIPS16 compaction: for the qualifying
instruction encodings the APPEND_ADD_COMPACT machine code generation
method is selected where APPEND_ADD_WITH_NOP otherwise would and tells
the code generator in `append_insn' to convert the regular form of an
instruction to its corresponding compact form.  For this the opcode is
tweaked as necessary and the microMIPS opcode table is scanned for the
matching updated instruction.  A non-$0 `rt' operand to BEQ and BNE
instructions is moved to the `rs' operand field of BEQZC and BNEZC
encodings as required.

Unlike with MIPS16 compaction however we need to handle out-of-distance
branch relaxation as well.  We do this by deferring the generation of
any delay-slot NOP required to relaxation made in `md_convert_frag', by
converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD
where a relaxed instruction is recorded.  Relaxation then, depending on
actual code produced, chooses between either using a compact branch or
jump encoding and emitting the NOP outstanding if no compact encoding is
possible.

For code simplicity's sake the relaxation pass is retained even if the
principle of preferring a compact encoding to a 16-bit branch/NOP pair
means, in the absence of out-of-range branch relaxation, that a single
compact branch machine code instruction will eventually be produced from
a given assembly source instruction.

	gas/
	* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
	(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
	(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
	(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
	(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
	(get_append_method): Also return APPEND_ADD_COMPACT for
	microMIPS instructions.
	(find_altered_mips16_opcode): Exclude macros from matching.
	Factor code out...
	(find_altered_opcode): ... to this new function.
	(find_altered_micromips_opcode): New function.
	(frag_branch_delay_slot_size): Likewise.
	(append_insn): Handle microMIPS branch/jump compaction.
	(macro_start): Likewise.
	(relaxed_micromips_32bit_branch_length): Likewise.
	(md_convert_frag): Likewise.
	* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
	for delay slot filling.
	* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
	delay slot filling.
	* testsuite/gas/mips/micromips-size-1.s: Likewise.
	* testsuite/gas/mips/micromips.l: Adjust line numbers.
	* testsuite/gas/mips/micromips-warn.l: Likewise.
	* testsuite/gas/mips/micromips-size-1.l: Likewise.
	* testsuite/gas/mips/micromips.d: Adjust padding.
	* testsuite/gas/mips/micromips-trap.d: Likewise.
	* testsuite/gas/mips/micromips-insn32.d: Likewise.
	* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
	* testsuite/gas/mips/micromips@beq.d: Update patterns for
	branch/jump compaction.
	* testsuite/gas/mips/micromips@bge.d: Likewise.
	* testsuite/gas/mips/micromips@bgeu.d: Likewise.
	* testsuite/gas/mips/micromips@blt.d: Likewise.
	* testsuite/gas/mips/micromips@bltu.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
	Likewise.
	* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
	* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
	* testsuite/gas/mips/micromips@relax.d: Likewise.
	* testsuite/gas/mips/micromips@relax-at.d: Likewise.
	* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
	* testsuite/gas/mips/branch-extern-2.d: Likewise.
	* testsuite/gas/mips/branch-extern-4.d: Likewise.
	* testsuite/gas/mips/branch-section-2.d: Likewise.
	* testsuite/gas/mips/branch-section-4.d: Likewise.
	* testsuite/gas/mips/branch-weak-2.d: Likewise.
	* testsuite/gas/mips/branch-weak-5.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
	Likewise.
	* testsuite/gas/mips/micromips-compact.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.

	ld/
	* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
	patterns for branch compaction.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
	Likewise.

	opcodes/
	* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
	"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
	"j".

2 files changed, 21 insertions, 7 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c218197..6090585 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
+	"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
+	"j".
+
 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 
         * arc-nps400-tbl.h: Change block comments to GNU format.
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index e182f47..dbbb792 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -305,9 +305,11 @@ const struct mips_opcode micromips_opcodes[] =
 {"b",			"mD",		    0xcc00,     0xfc00,	UBD,			0,		I1,		0,	0 },
 {"b",			"p",		0x94000000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 }, /* beq 0, 0 */
 {"b",			"p",		0x40400000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 }, /* bgez 0 */
+/* BC is next to B so that we easily find it when converting a normal
+   branch to a compact one.  */
+{"bc",			"p",		0x40e00000, 0xffff0000,	NODS,			INSN2_ALIAS|UBR,  I1,		0,	0 }, /* beqzc 0 */
 {"bal",			"p",		0x40600000, 0xffff0000,	WR_31|UBD,		INSN2_ALIAS|BD32, I1,		0,	0 }, /* bgezal 0 */
 {"bals",		"p",		0x42600000, 0xffff0000,	WR_31|UBD,		INSN2_ALIAS|BD16, I1,		0,	0 }, /* bgezals 0 */
-{"bc",			"p",		0x40e00000, 0xffff0000,	NODS,			INSN2_ALIAS|UBR,  I1,		0,	0 }, /* beqzc 0 */
 {"abs",			"d,v",		0,    (int) M_ABS,	INSN_MACRO,		0,		I1,		0,	0 },
 {"abs.d",		"T,V",		0x5400237b, 0xfc00ffff,	WR_1|RD_2|FP_D,		0,		I1,		0,	0 },
 {"abs.s",		"T,V",		0x5400037b, 0xfc00ffff,	WR_1|RD_2|FP_S,		0,		I1,		0,	0 },
@@ -366,12 +368,14 @@ const struct mips_opcode micromips_opcodes[] =
 {"bc2tl",		"N,p",		0,    (int) M_BC2TL,	INSN_MACRO,		0,		I1,		0,	0 },
 {"beqz",		"md,mE",	    0x8c00,     0xfc00,	RD_1|CBD,		0,		I1,		0,	0 },
 {"beqz",		"s,p",		0x94000000, 0xffe00000,	RD_1|CBD,		0,		I1,		0,	0 },
-{"beqzc",		"s,p",		0x40e00000, 0xffe00000,	RD_1|NODS,		CBR,		I1,		0,	0 },
 {"beqzl",		"s,p",		0,    (int) M_BEQL,	INSN_MACRO,		0,		I1,		0,	0 },
 {"beq",			"md,mz,mE",	    0x8c00,     0xfc00,	RD_1|CBD,		0,		I1,		0,	0 }, /* beqz */
 {"beq",			"mz,md,mE",	    0x8c00,     0xfc00,	RD_2|CBD,		0,		I1,		0,	0 }, /* beqz */
 {"beq",			"s,t,p",	0x94000000, 0xfc000000,	RD_1|RD_2|CBD,		0,		I1,		0,	0 },
 {"beq",			"s,I,p",	0,    (int) M_BEQ_I,	INSN_MACRO,		0,		I1,		0,	0 },
+/* BEQZC is next to BEQ so that we easily find it when converting a normal
+   branch to a compact one.  */
+{"beqzc",		"s,p",		0x40e00000, 0xffe00000,	RD_1|NODS,		CBR,		I1,		0,	0 },
 {"beql",		"s,t,p",	0,    (int) M_BEQL,	INSN_MACRO,		0,		I1,		0,	0 },
 {"beql",		"s,I,p",	0,    (int) M_BEQL_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bge",			"s,t,p",	0,    (int) M_BGE,	INSN_MACRO,		0,		I1,		0,	0 },
@@ -422,12 +426,14 @@ const struct mips_opcode micromips_opcodes[] =
 {"bltzall",		"s,p",		0,    (int) M_BLTZALL,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bnez",		"md,mE",	    0xac00,     0xfc00,	RD_1|CBD,		0,		I1,		0,	0 },
 {"bnez",		"s,p",		0xb4000000, 0xffe00000,	RD_1|CBD,		0,		I1,		0,	0 },
-{"bnezc",		"s,p",		0x40a00000, 0xffe00000,	RD_1|NODS,		CBR,		I1,		0,	0 },
 {"bnezl",		"s,p",		0,    (int) M_BNEL,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bne",			"md,mz,mE",	    0xac00,     0xfc00,	RD_1|CBD,		0,		I1,		0,	0 }, /* bnez */
 {"bne",			"mz,md,mE",	    0xac00,     0xfc00,	RD_2|CBD,		0,		I1,		0,	0 }, /* bnez */
 {"bne",			"s,t,p",	0xb4000000, 0xfc000000,	RD_1|RD_2|CBD,		0,		I1,		0,	0 },
 {"bne",			"s,I,p",	0,    (int) M_BNE_I,	INSN_MACRO,		0,		I1,		0,	0 },
+/* BNEZC is next to BNE so that we easily find it when converting a normal
+   branch to a compact one.  */
+{"bnezc",		"s,p",		0x40a00000, 0xffe00000,	RD_1|NODS,		CBR,		I1,		0,	0 },
 {"bnel",		"s,t,p",	0,    (int) M_BNEL,	INSN_MACRO,		0,		I1,		0,	0 },
 {"bnel",		"s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"break",		"",		    0x4680,     0xffff,	TRAP,			0,		I1,		0,	0 },
@@ -697,10 +703,6 @@ const struct mips_opcode micromips_opcodes[] =
 /* This macro is after the real instruction so that it only matches with
    -minsn32.  */
 {"jraddiusp",		"mP",		0,   (int) M_JRADDIUSP,	INSN_MACRO,		0,		I1,		0,	0 },
-{"jrc",			"mj",		    0x45a0,     0xffe0,	RD_1|NODS,		UBR,		I1,		0,	0 },
-/* This macro is after the real instruction so that it only matches with
-   -minsn32.  */
-{"jrc",			"s",		0,    (int) M_JRC,	INSN_MACRO,		0,		I1,		0,	0 },
 {"jr.hb",		"s",		0x00001f3c, 0xffe0ffff,	RD_1|UBD,		BD32,		I1,		0,	0 }, /* jalr.hb */
 {"jrs.hb",		"s",		0x00005f3c, 0xffe0ffff,	RD_1|UBD,		BD16,		I1,		0,	0 }, /* jalrs.hb */
 {"j",			"mj",		    0x4580,     0xffe0,	RD_1|UBD,		0,		I1,		0,	0 }, /* jr */
@@ -712,6 +714,12 @@ const struct mips_opcode micromips_opcodes[] =
    assembler, but will never match user input (because the line above
    will match first).  */
 {"j",			"a",		0xd4000000, 0xfc000000,	UBD,			0,		I1,		0,	0 },
+/* JRC is close to JR and J so that we easily find it when converting
+   a normal jump to a compact one.  */
+{"jrc",			"mj",		    0x45a0,     0xffe0,	RD_1|NODS,		UBR,		I1,		0,	0 },
+/* This macro is after the real instruction so that it only matches with
+   -minsn32.  */
+{"jrc",			"s",		0,    (int) M_JRC,	INSN_MACRO,		0,		I1,		0,	0 },
 {"jalr",		"mj",		    0x45c0,     0xffe0,	RD_1|WR_31|UBD,		BD32,		I1,		0,	0 },
 {"jalr",		"my,mj",	    0x45c0,     0xffe0,	RD_2|WR_31|UBD,		BD32,		I1,		0,	0 },
 {"jalr",		"s",		0x03e00f3c, 0xffe0ffff,	RD_1|WR_31|UBD,		BD32,		I1,		0,	0 },