Add system register and embedded debug register support.

Add two more as test files for user special and system register.
Fix typo.

2013-12-17  Kuan-Lin Chen  <kuanlinchentw@gmail.com>

	* gas/nds32/nds32.exp: Add system and user special register tests.
	* gas/nds32/sys-reg.s: New test.
	* gas/nds32/sys-reg.d: Likewise.
	* gas/nds32/usr-spe-reg.s: Likewise.
	* gas/nds32/usr-spe-reg.d: Likewise.
	* gas/nds32/alu-2.d: Delete the new blank line at EOF.
	* gas/nds32/br-1.d: Likewise.
	* gas/nds32/br-2.d: Likewise.
	* gas/nds32/ji-jr.d: Likewise.
	* gas/nds32/lsi.d: Likewise.
	* nds32-dis.c (sr_map): Add system register table for disassembling.
	(usr_map): Fix typo.
	* nds32-asm.c (keyword_sr): Add embedded debug registers.

3 files changed, 147 insertions, 6 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d944dfd..8a9d7e6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2013-12-17  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+	* nds32-dis.c (sr_map): Add system register table for disassembling.
+	(usr_map): Fix typo.
+	* nds32-asm.c (keyword_sr): Add embedded debug registers.
+
 2013-12-17  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 
 	* i386-dis.c (MOD_FF_REG_3): New.
diff --git a/opcodes/nds32-asm.c b/opcodes/nds32-asm.c
index 958301a..d7681bf 100644
--- a/opcodes/nds32-asm.c
+++ b/opcodes/nds32-asm.c
@@ -858,6 +858,54 @@ static const keyword_t keyword_sr[] =
   {"prusr_acc_ctl", SRIDX (4, 4, 0), 0},
   {"fucpr", SRIDX (4, 5, 0), 0}, {"fucop_ctl", SRIDX (4, 5, 0), 0},
 
+  {"dr0", SRIDX (3, 0, 0), 0}, {"bpc0", SRIDX (3, 0, 0), 0},
+  {"dr1", SRIDX (3, 0, 1), 0}, {"bpc1", SRIDX (3, 0, 1), 0},
+  {"dr2", SRIDX (3, 0, 2), 0}, {"bpc2", SRIDX (3, 0, 2), 0},
+  {"dr3", SRIDX (3, 0, 3), 0}, {"bpc3", SRIDX (3, 0, 3), 0},
+  {"dr4", SRIDX (3, 0, 4), 0}, {"bpc4", SRIDX (3, 0, 4), 0},
+  {"dr5", SRIDX (3, 0, 5), 0}, {"bpc5", SRIDX (3, 0, 5), 0},
+  {"dr6", SRIDX (3, 0, 6), 0}, {"bpc6", SRIDX (3, 0, 6), 0},
+  {"dr7", SRIDX (3, 0, 7), 0}, {"bpc7", SRIDX (3, 0, 7), 0},
+  {"dr8", SRIDX (3, 1, 0), 0}, {"bpa0", SRIDX (3, 1, 0), 0},
+  {"dr9", SRIDX (3, 1, 1), 0}, {"bpa1", SRIDX (3, 1, 1), 0},
+  {"dr10", SRIDX (3, 1, 2), 0}, {"bpa2", SRIDX (3, 1, 2), 0},
+  {"dr11", SRIDX (3, 1, 3), 0}, {"bpa3", SRIDX (3, 1, 3), 0},
+  {"dr12", SRIDX (3, 1, 4), 0}, {"bpa4", SRIDX (3, 1, 4), 0},
+  {"dr13", SRIDX (3, 1, 5), 0}, {"bpa5", SRIDX (3, 1, 5), 0},
+  {"dr14", SRIDX (3, 1, 6), 0}, {"bpa6", SRIDX (3, 1, 6), 0},
+  {"dr15", SRIDX (3, 1, 7), 0}, {"bpa7", SRIDX (3, 1, 7), 0},
+  {"dr16", SRIDX (3, 2, 0), 0}, {"bpam0", SRIDX (3, 2, 0), 0},
+  {"dr17", SRIDX (3, 2, 1), 0}, {"bpam1", SRIDX (3, 2, 1), 0},
+  {"dr18", SRIDX (3, 2, 2), 0}, {"bpam2", SRIDX (3, 2, 2), 0},
+  {"dr19", SRIDX (3, 2, 3), 0}, {"bpam3", SRIDX (3, 2, 3), 0},
+  {"dr20", SRIDX (3, 2, 4), 0}, {"bpam4", SRIDX (3, 2, 4), 0},
+  {"dr21", SRIDX (3, 2, 5), 0}, {"bpam5", SRIDX (3, 2, 5), 0},
+  {"dr22", SRIDX (3, 2, 6), 0}, {"bpam6", SRIDX (3, 2, 6), 0},
+  {"dr23", SRIDX (3, 2, 7), 0}, {"bpam7", SRIDX (3, 2, 7), 0},
+  {"dr24", SRIDX (3, 3, 0), 0}, {"bpv0", SRIDX (3, 3, 0), 0},
+  {"dr25", SRIDX (3, 3, 1), 0}, {"bpv1", SRIDX (3, 3, 1), 0},
+  {"dr26", SRIDX (3, 3, 2), 0}, {"bpv2", SRIDX (3, 3, 2), 0},
+  {"dr27", SRIDX (3, 3, 3), 0}, {"bpv3", SRIDX (3, 3, 3), 0},
+  {"dr28", SRIDX (3, 3, 4), 0}, {"bpv4", SRIDX (3, 3, 4), 0},
+  {"dr29", SRIDX (3, 3, 5), 0}, {"bpv5", SRIDX (3, 3, 5), 0},
+  {"dr30", SRIDX (3, 3, 6), 0}, {"bpv6", SRIDX (3, 3, 6), 0},
+  {"dr31", SRIDX (3, 3, 7), 0}, {"bpv7", SRIDX (3, 3, 7), 0},
+  {"dr32", SRIDX (3, 4, 0), 0}, {"bpcid0", SRIDX (3, 4, 0), 0},
+  {"dr33", SRIDX (3, 4, 1), 0}, {"bpcid1", SRIDX (3, 4, 1), 0},
+  {"dr34", SRIDX (3, 4, 2), 0}, {"bpcid2", SRIDX (3, 4, 2), 0},
+  {"dr35", SRIDX (3, 4, 3), 0}, {"bpcid3", SRIDX (3, 4, 3), 0},
+  {"dr36", SRIDX (3, 4, 4), 0}, {"bpcid4", SRIDX (3, 4, 4), 0},
+  {"dr37", SRIDX (3, 4, 5), 0}, {"bpcid5", SRIDX (3, 4, 5), 0},
+  {"dr38", SRIDX (3, 4, 6), 0}, {"bpcid6", SRIDX (3, 4, 6), 0},
+  {"dr39", SRIDX (3, 4, 7), 0}, {"bpcid7", SRIDX (3, 4, 7), 0},
+  {"dr40", SRIDX (3, 5, 0), 0}, {"edm_cfg", SRIDX (3, 5, 0), 0},
+  {"dr41", SRIDX (3, 6, 0), 0}, {"edmsw", SRIDX (3, 6, 0), 0},
+  {"dr42", SRIDX (3, 7, 0), 0}, {"edm_ctl", SRIDX (3, 7, 0), 0},
+  {"dr43", SRIDX (3, 8, 0), 0}, {"edm_dtr", SRIDX (3, 8, 0), 0},
+  {"dr44", SRIDX (3, 9, 0), 0}, {"bpmtc", SRIDX (3, 9, 0), 0},
+  {"dr45", SRIDX (3, 10, 0), 0}, {"dimbr", SRIDX (3, 10, 0), 0},
+  {"dr46", SRIDX (3, 14, 0), 0}, {"tecr0", SRIDX (3, 14, 0), 0},
+  {"dr47", SRIDX (3, 14, 1), 0}, {"tecr1", SRIDX (3, 14, 1), 0},
   {NULL,0 ,0}
 };
 
diff --git a/opcodes/nds32-dis.c b/opcodes/nds32-dis.c
index 25a1aad..c732e84 100644
--- a/opcodes/nds32-dis.c
+++ b/opcodes/nds32-dis.c
@@ -167,6 +167,9 @@ static const char *mnemonic_fd2_cmp[] =
   "fcmpled", "fcmpled.e", "fcmpund", "fcmpund.e"
 };
 
+/* Register name table.  */
+/* General purpose register.  */
+
 static const char *gpr_map[] =
 {
   "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7",
@@ -175,10 +178,12 @@ static const char *gpr_map[] =
   "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp"
 };
 
+/* User special register.  */
+
 static const char *usr_map[][32] =
 {
   {
-    "d0,lo", "d0.hi", "d1,lo", "d1,hi", "4",  "5",  "6",  "7",
+    "d0.lo", "d0.hi", "d1.lo", "d1.hi", "4",  "5",  "6",  "7",
     "8",     "9",     "10",    "11",    "12", "13", "14", "15",
     "16",    "17",    "18",    "19",    "20", "21", "22", "23",
     "24",    "25",    "26",    "27",    "28", "29", "30", "pc"
@@ -187,12 +192,94 @@ static const char *usr_map[][32] =
     "DMA_CFG",     "DMA_GCSW",    "DMA_CHNSEL", "DMA_ACT",    "DMA_SETUP",
     "DMA_ISADDR",  "DMA_ESADDR",  "DMA_TCNT",   "DMA_STATUS", "DMA_2DSET",
     "10",          "11",          "12",         "13",         "14",
-    "15",          "16,",         "17",         "18",         "19",
-    "20",          "21",          "22",         "23",         "24,",
+    "15",          "16",          "17",         "18",         "19",
+    "20",          "21",          "22",         "23",         "24",
     "DMA_2DSCTL"
   },
   {
-    "PFMC0", "PFMC1", "PFMC2", "3", "PFMCTL"
+    "PFMC0", "PFMC1", "PFMC2", "3", "PFM_CTL"
+  }
+};
+
+/* System register.  */
+/* Major Minor Extension.  */
+static const char *sr_map[8][16][8] =
+{
+  {
+    {"CPU_VER", "CORE_ID"},
+    {"ICM_CFG"},
+    {"DCM_CFG"},
+    {"MMU_CFG"},
+    {"MSC_CFG"}
+  },
+  {
+    {"PSW", "IPSW", "P_IPSW"},
+    {"0", "IVB", "INT_CTRL"},
+    {"0", "EVA", "P_EVA"},
+    {"0", "ITYPE", "P_ITYPE"},
+    {"0", "MERR"},
+    {"0", "IPC", "P_IPC", "OIPC"},
+    {"0", "1", "P_P0"},
+    {"0", "1", "P_P1"},
+    {"INT_MASK", "INT_MASK2"},
+    {"INT_PEND", "INT_PEND2", "2", "3", "INT_TRIGGER"},
+    {"SP_USR", "SP_PRIV"},
+    {"INT_PRI", "INT_PRI2"}
+  },
+  {
+    {"MMU_CTL"},
+    {"L1_PPTB"},
+    {"TLB_VPN"},
+    {"TLB_DATA"},
+    {"TLB_MISC"},
+    {"VLPT_IDX"},
+    {"ILMB"},
+    {"DLMB"},
+    {"CACHE_CTL"},
+    {"HSMP_SADDR", "HSMP_EADDR"},
+    {"0"},
+    {"0"},
+    {"0"},
+    {"0"},
+    {"0"},
+    {"SDZ_CTL", "MISC_CTL"}
+  },
+  {
+    {"BPC0", "BPC1", "BPC2", "BPC3", "BPC4", "BPC5", "BPC6", "BPC7"},
+    {"BPA0", "BPA1", "BPA2", "BPA3", "BPA4", "BPA5", "BPA6", "BPA7"},
+    {"BPAM0", "BPAM1", "BPAM2", "BPAM3", "BPAM4", "BPAM5", "BPAM6", "BPAM7"},
+    {"BPV0", "BPV1", "BPV2", "BPV3", "BPV4", "BPV5", "BPV6", "BPV7"},
+    {"BPCID0", "BPCID1", "BPCID2", "BPCID3", "BPCID4", "BPCID5", "BPCID6", "BPCID7"},
+    {"EDM_CFG"},
+    {"EDMSW"},
+    {"EDM_CTL"},
+    {"EDM_DTR"},
+    {"BPMTC"},
+    {"DIMBR"},
+    {"EDM_PROBE"},
+    {"0"},
+    {"0"},
+    {"TECR0", "TECR1"}
+  },
+  {
+    {"PFMC0", "PFMC1", "PFMC2"},
+    {"PFM_CTL"},
+    {"0"},
+    {"0"},
+    {"PRUSR_ACC_CTL"},
+    {"FUCOP_CTL"}
+  },
+  {
+    {"DMA_CFG"},
+    {"DMA_GCSW"},
+    {"DMA_CHNSEL"},
+    {"DMA_ACT"},
+    {"DMA_SETUP"},
+    {"DMA_ISADDR"},
+    {"DMA_ESADDR"},
+    {"DMA_TCNT"},
+    {"DMA_STATUS"},
+    {"DMA_2DSET", "DMA_2DSCTL"}
   }
 };
 
@@ -763,8 +850,8 @@ print_insn32_misc (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info,
     case 0x2:			/* mfsr */
     case 0x3:			/* mtsr */
       /* FIXME: setend, setgie.  */
-      id = __GF (insn, 10, 10);
-      func (stream, "%s\t%s, %d", mnemonic_misc[op], gpr_map[rt], id);
+      func (stream, "%s\t%s, $%s", mnemonic_misc[op], gpr_map[rt],
+	    sr_map[__GF(insn, 17, 3)][__GF(insn, 13, 4)][__GF(insn, 10, 3)]);
       return;
     case 0x6:			/* teqz */
     case 0x7:			/* tnez */