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authorNick Clifton <nickc@redhat.com>2012-05-15 12:55:51 +0000
committerNick Clifton <nickc@redhat.com>2012-05-15 12:55:51 +0000
commit6927f98292aaa6f7fcb3152d5d902758538e626c (patch)
treeb459b91d4d7f001cc57214f7c4a554b7ab3cb192 /opcodes
parent9cc815f56d3c2f1fc8f033b869693975bceb9633 (diff)
downloadgdb-6927f98292aaa6f7fcb3152d5d902758538e626c.zip
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* config/tc-m68hc11.c: Add S12X and XGATE co-processor support.
Add option to offset S12 addresses into XGATE memory space. Tweak target flags to match other tools. (i.e. -m m68hc11). * doc/as.texinfo: Mention new options. * doc/c-m68hc11.texi: Document new options. * NEWS: Mention new support. * archures.c: Add bfd_arch_m9s12x and bfd_arch_m9s12xg. * config.bfd: Likewise. * cpu-m9s12x.c: New. * cpu-m9s12xg.c: New. * elf32-m68hc12.c: Add S12X and XGATE co-processor support. Add option to offset S12 addresses into XGATE memory space. Fix carry bug in IMM16 (IMM8 low/high) relocate. * Makefile.am (ALL_MACHINES): Add cpu-m9s12x and cpu-m9s12xg. (ALL_MACHINES_CFILES): Likewise. * reloc.c: Add S12X relocs. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * gas/m68hc11/insns9s12x.s: New * gas/m68hc11/insns9s12x.d: New * gas/m68hc11/hexprefix.s: New * gas/m68hc11/hexprefix.d: New * gas/m68hc11/9s12x-exg-sex-tfr.s: New * gas/m68hc11/9s12x-exg-sex-tfr.d: New * gas/m68hc11/insns9s12xg.s: New * gas/m68hc11/insns9s12xg.d: New * gas/m68hc11/9s12x-mov.s: New * gas/m68hc11/9s12x-mov.d: New * gas/m68hc11/m68hc11.exp: Updated * gas/m68hc11/*.d: Brought in line with changed objdump output. * gas/all/gas.exp: XFAIL all hc11/12 targets for redef2,3. * gas/elf/elf.exp: XFAIL all hc11/12 targets for redef. * gas/elf/dwarf2-1.d: Skip for hc11/12 targets. * gas/elf/dwarf2-2.d: Likewise. * ld-m68hc11/xgate-link.s: New. * ld-m68hc11/xgate-link.d: New. * ld-m68hc11/xgate-offset.s: New. * ld-m68hc11/xgate-offset.d: New. * ld-m68hc11/xgate1.s: New. * ld-m68hc11/xgate1.d: New. * ld-m68hc11/xgate2.s: New. * ld-m68hc11/m68hc11.exp: Updated. * ld-m68hc11/*.d: Brought in line with changed objdump output. * ld-gc/gc.exp: Update CFLAGS for m68hc11. * ld-plugin/plugin.exp: Likewise. * ld-srec/srec.exp: XFAIL for m68hc11 and m68hc12. * configure.in: Add S12X and XGATE co-processor support to m68hc11 target. * disassemble.c: Likewise. * configure: Regenerate. * m68hc11-dis.c: Make objdump output more consistent, use hex instead of decimal and use 0x prefix for hex. * m68hc11-opc.c: Add S12X and XGATE opcodes. * dis-asm.h (print_insn_m9s12x): Prototype. (print_insn_m9s12xg): Prototype. * m68hc11.h (R_M68HC12_16B, R_M68HC12_PCREL_9, R_M68HC12_PCREL_10) R_M68HC12_HI8XG, R_M68HC12_LO8XG): New relocations. (E_M68HC11_XGATE_RAMOFFSET): Define. * m68hc11.h: Add XGate definitions. (struct m68hc11_opcode): Add xg_mask field.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog11
-rwxr-xr-xopcodes/configure2
-rw-r--r--opcodes/configure.in2
-rw-r--r--opcodes/disassemble.c9
-rw-r--r--opcodes/m68hc11-dis.c494
-rw-r--r--opcodes/m68hc11-opc.c2450
6 files changed, 1898 insertions, 1070 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e8a816d..abfec32 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
+ Stephane Carrez <stcarrez@nerim.fr>
+
+ * configure.in: Add S12X and XGATE co-processor support to m68hc11
+ target.
+ * disassemble.c: Likewise.
+ * configure: Regenerate.
+ * m68hc11-dis.c: Make objdump output more consistent, use hex
+ instead of decimal and use 0x prefix for hex.
+ * m68hc11-opc.c: Add S12X and XGATE opcodes.
+
2012-05-14 James Lemke <jwlemke@codesourcery.com>
* ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
diff --git a/opcodes/configure b/opcodes/configure
index 1613ae0..9426e7e 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12468,6 +12468,8 @@ if test x${all_targets} = xfalse ; then
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
+ bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
+ bfd_m9s12xg_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 1d3f2d9..9c84816 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -251,6 +251,8 @@ if test x${all_targets} = xfalse ; then
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
+ bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
+ bfd_m9s12xg_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 7ff5f22..3dad64b 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -248,13 +248,20 @@ disassembler (abfd)
disassemble = print_insn_m32r;
break;
#endif
-#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12)
+#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \
+ || defined(ARCH_9s12x) || defined(ARCH_m9s12xg)
case bfd_arch_m68hc11:
disassemble = print_insn_m68hc11;
break;
case bfd_arch_m68hc12:
disassemble = print_insn_m68hc12;
break;
+ case bfd_arch_m9s12x:
+ disassemble = print_insn_m9s12x;
+ break;
+ case bfd_arch_m9s12xg:
+ disassemble = print_insn_m9s12xg;
+ break;
#endif
#ifdef ARCH_m68k
case bfd_arch_m68k:
diff --git a/opcodes/m68hc11-dis.c b/opcodes/m68hc11-dis.c
index f6d6184..98ef4d9 100644
--- a/opcodes/m68hc11-dis.c
+++ b/opcodes/m68hc11-dis.c
@@ -1,7 +1,8 @@
/* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly
- Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007
+ Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2012
Free Software Foundation, Inc.
Written by Stephane Carrez (stcarrez@nerim.fr)
+ XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk)
This file is part of the GNU opcodes library.
@@ -28,15 +29,18 @@
#define PC_REGNUM 3
-static const char *const reg_name[] = {
+static const char *const reg_name[] =
+{
"X", "Y", "SP", "PC"
};
-static const char *const reg_src_table[] = {
+static const char *const reg_src_table[] =
+{
"A", "B", "CCR", "TMP3", "D", "X", "Y", "SP"
};
-static const char *const reg_dst_table[] = {
+static const char *const reg_dst_table[] =
+{
"A", "B", "CCR", "TMP2", "D", "X", "Y", "SP"
};
@@ -45,7 +49,7 @@ static const char *const reg_dst_table[] = {
/* Prototypes for local functions. */
static int read_memory (bfd_vma, bfd_byte *, int, struct disassemble_info *);
static int print_indexed_operand (bfd_vma, struct disassemble_info *,
- int*, int, int, bfd_vma);
+ int*, int, int, bfd_vma, int);
static int print_insn (bfd_vma, struct disassemble_info *, int);
static int
@@ -71,7 +75,7 @@ read_memory (bfd_vma memaddr, bfd_byte* buffer, int size,
static int
print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info,
int* indirect, int mov_insn, int pc_offset,
- bfd_vma endaddr)
+ bfd_vma endaddr, int arch)
{
bfd_byte buffer[4];
int reg;
@@ -98,12 +102,14 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info,
/* 68HC12 requires an adjustment for movb/movw pc relative modes. */
if (reg == PC_REGNUM && info->mach == bfd_mach_m6812 && mov_insn)
sval += pc_offset;
- (*info->fprintf_func) (info->stream, "%d,%s",
- (int) sval, reg_name[reg]);
+ (*info->fprintf_func) (info->stream, "0x%x,%s",
+ (unsigned short) sval, reg_name[reg]);
if (reg == PC_REGNUM)
{
(* info->fprintf_func) (info->stream, " {");
+ if (info->symtab_size > 0) /* Avoid duplicate 0x from core binutils. */
+ (*info->fprintf_func) (info->stream, "0x");
(* info->print_address_func) (endaddr + sval, info);
(* info->fprintf_func) (info->stream, "}");
}
@@ -128,7 +134,7 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info,
mode = "+";
}
(*info->fprintf_func) (info->stream, "%d,%s%s%s",
- (int) sval,
+ (unsigned short) sval,
(buffer[0] & 0x10 ? "" : mode),
reg_name[reg], (buffer[0] & 0x10 ? mode : ""));
}
@@ -136,12 +142,12 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info,
/* [n,r] 16-bits offset indexed indirect. */
else if ((buffer[0] & 0x07) == 3)
{
- if (mov_insn)
- {
- (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>",
- buffer[0] & 0x0ff);
- return 0;
- }
+ if ((mov_insn) && (!(arch & cpu9s12x)))
+ {
+ (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>",
+ buffer[0] & 0x0ff);
+ return 0;
+ }
reg = (buffer[0] >> 3) & 0x03;
status = read_memory (memaddr + pos, &buffer[0], 2, info);
if (status != 0)
@@ -151,7 +157,7 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info,
pos += 2;
sval = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
- (*info->fprintf_func) (info->stream, "[%u,%s]",
+ (*info->fprintf_func) (info->stream, "[0x%x,%s]",
sval & 0x0ffff, reg_name[reg]);
if (indirect)
*indirect = 1;
@@ -160,12 +166,13 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info,
/* n,r with 9 and 16 bit signed constant. */
else if ((buffer[0] & 0x4) == 0)
{
- if (mov_insn)
- {
- (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>",
- buffer[0] & 0x0ff);
- return 0;
- }
+ if ((mov_insn) && (!(arch & cpu9s12x)))
+ {
+ (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>",
+ buffer[0] & 0x0ff);
+ return 0;
+ }
+
reg = (buffer[0] >> 3) & 0x03;
status = read_memory (memaddr + pos,
&buffer[1], (buffer[0] & 0x2 ? 2 : 1), info);
@@ -188,11 +195,11 @@ print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info,
pos++;
endaddr++;
}
- (*info->fprintf_func) (info->stream, "%d,%s",
- (int) sval, reg_name[reg]);
+ (*info->fprintf_func) (info->stream, "0x%x,%s",
+ (unsigned short) sval, reg_name[reg]);
if (reg == PC_REGNUM)
{
- (* info->fprintf_func) (info->stream, " {");
+ (* info->fprintf_func) (info->stream, " {0x");
(* info->print_address_func) (endaddr + sval, info);
(* info->fprintf_func) (info->stream, "}");
}
@@ -230,18 +237,114 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
{
int status;
bfd_byte buffer[4];
- unsigned char code;
+ unsigned int code;
long format, pos, i;
short sval;
const struct m68hc11_opcode *opcode;
+ if (arch & cpuxgate)
+ {
+ int val;
+ /* Get two bytes as all XGATE instructions are 16bit. */
+ status = read_memory (memaddr, buffer, 2, info);
+ if (status != 0)
+ return status;
+
+ format = 0;
+ code = (buffer[0] << 8) + buffer[1];
+
+ /* Scan the opcode table until we find the opcode
+ with the corresponding page. */
+ opcode = m68hc11_opcodes;
+ for (i = 0; i < m68hc11_num_opcodes; i++, opcode++)
+ {
+ if ((opcode->opcode != (code & opcode->xg_mask)) || (opcode->arch != cpuxgate))
+ continue;
+ /* We have found the opcode. Extract the operand and print it. */
+ (*info->fprintf_func) (info->stream, "%s", opcode->name);
+ format = opcode->format;
+ if (format & (M68XG_OP_NONE))
+ {
+ /* Nothing to print. */
+ }
+ else if (format & M68XG_OP_IMM3)
+ (*info->fprintf_func) (info->stream, " #0x%x", (code >> 8) & 0x7);
+ else if (format & M68XG_OP_R_R)
+ (*info->fprintf_func) (info->stream, " R%x, R%x",
+ (code >> 8) & 0x7, (code >> 5) & 0x7);
+ else if (format & M68XG_OP_R_R_R)
+ (*info->fprintf_func) (info->stream, " R%x, R%x, R%x",
+ (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7);
+ else if (format & M68XG_OP_RD_RB_RI)
+ (*info->fprintf_func) (info->stream, " R%x, (R%x, R%x)",
+ (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7);
+ else if (format & M68XG_OP_RD_RB_RIp)
+ (*info->fprintf_func) (info->stream, " R%x, (R%x, R%x+)",
+ (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7);
+ else if (format & M68XG_OP_RD_RB_mRI)
+ (*info->fprintf_func) (info->stream, " R%x, (R%x, -R%x)",
+ (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7);
+ else if (format & M68XG_OP_R_R_OFFS5)
+ (*info->fprintf_func) (info->stream, " R%x, (R%x, #0x%x)",
+ (code >> 8) & 0x7, (code >> 5) & 0x7, code & 0x1f);
+ else if (format & M68XG_OP_R_IMM8)
+ (*info->fprintf_func) (info->stream, " R%x, #0x%02x",
+ (code >> 8) & 0x7, code & 0xff);
+ else if (format & M68XG_OP_R_IMM4)
+ (*info->fprintf_func) (info->stream, " R%x, #0x%x",
+ (code >> 8) & 0x7, (code & 0xf0) >> 4);
+ else if (format & M68XG_OP_REL9)
+ {
+ (*info->fprintf_func) (info->stream, " 0x");
+ val = (buffer[0] & 0x1) ? buffer[1] | 0xFFFFFF00 : buffer[1];
+ (*info->print_address_func) (memaddr + (val << 1) + 2, info);
+ }
+ else if (format & M68XG_OP_REL10)
+ {
+ (*info->fprintf_func) (info->stream, " 0x");
+ val = (buffer[0] << 8) | (unsigned int) buffer[1];
+ if (val & 0x200)
+ val |= 0xfffffc00;
+ else
+ val &= 0x000001ff;
+ (*info->print_address_func) (memaddr + (val << 1) + 2, info);
+ }
+ else if ((code & 0x00ff) == 0x00f8)
+ (*info->fprintf_func) (info->stream, " R%x, CCR", (code >> 8) & 0x7);
+ else if ((code & 0x00ff) == 0x00f9)
+ (*info->fprintf_func) (info->stream, " CCR, R%x", (code >> 8) & 0x7);
+ else if ((code & 0x00ff) == 0x0)
+ (*info->fprintf_func) (info->stream, " R%x, PC", (code >> 8) & 0x7);
+ else if (format & M68XG_OP_R)
+ {
+ /* Special cases for TFR. */
+ if ((code & 0xf8ff) == 0x00f8)
+ (*info->fprintf_func) (info->stream, " R%x, CCR", (code >> 8) & 0x7);
+ else if ((code & 0xf8ff) == 0x00f9)
+ (*info->fprintf_func) (info->stream, " CCR, R%x", (code >> 8) & 0x7);
+ else if ((code & 0xf8ff) == 0x00fa)
+ (*info->fprintf_func) (info->stream, " R%x, PC", (code >> 8) & 0x7);
+ else
+ (*info->fprintf_func) (info->stream, " R%x", (code >> 8) & 0x7);
+ }
+ else
+ /* Opcode not recognized. */
+ (*info->fprintf_func) (info->stream, "Not yet handled TEST .byte\t0x%04x", code);
+ return 2;
+ }
+
+ /* Opcode not recognized. */
+ (*info->fprintf_func) (info->stream, ".byte\t0x%04x", code);
+ return 2; /* Everything is two bytes. */
+ }
+
+ /* HC11 and HC12. */
+
/* Get first byte. Only one at a time because we don't know the
size of the insn. */
status = read_memory (memaddr, buffer, 1, info);
if (status != 0)
- {
- return status;
- }
+ return status;
format = 0;
code = buffer[0];
@@ -269,13 +372,11 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
{
status = read_memory (memaddr + pos, &buffer[1], 1, info);
if (status != 0)
- {
- return status;
- }
+ return status;
+
code = buffer[1];
}
-
/* Look first for a 68HC12 alias. All of them are 2-bytes long and
in page 1. There is no operand to print. We read the second byte
only when we have a possible match. */
@@ -374,6 +475,10 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
&& (((buffer[0] & 0x07) >= 3 && (buffer[0] & 7) <= 7))
&& ((buffer[0] & 0x0f0) <= 0x20))
break;
+ if ((opcode[j].format & M6812_OP_SEX_MARKER)
+ && (arch & cpu9s12x)
+ && ((buffer[0] == 0x4d) || (buffer[0] == 0x4e)))
+ break;
if (opcode[j].format & M6812_OP_TFR_MARKER
&& !(buffer[0] & 0x80))
break;
@@ -393,73 +498,107 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
}
/* The movb and movw must be handled in a special way...
- The source constant 'ii' is not always at the same place.
- This is the same for the destination for the post-indexed byte.
- The 'offset' is used to do the appropriate correction.
-
- offset offset
- for constant for destination
- movb 18 OB ii hh ll 0 0
- 18 08 xb ii 1 -1
- 18 0C hh ll hh ll 0 0
- 18 09 xb hh ll 1 -1
- 18 0D xb hh ll 0 0
- 18 0A xb xb 0 0
-
- movw 18 03 jj kk hh ll 0 0
- 18 00 xb jj kk 1 -1
- 18 04 hh ll hh ll 0 0
- 18 01 xb hh ll 1 -1
- 18 05 xb hh ll 0 0
- 18 02 xb xb 0 0
-
- After the source operand is read, the position 'pos' is incremented
- this explains the negative offset for destination.
-
- movb/movw above are the only instructions with this matching
- format. */
+ The source constant 'ii' is not always at the same place.
+ This is the same for the destination for the post-indexed byte.
+ The 'offset' is used to do the appropriate correction.
+
+ offset offset
+ for constant for destination
+ movb 18 OB ii hh ll 0 0
+ 18 08 xb ii 1 -1
+ 18 08 xb ff ii 2 1 9 bit
+ 18 08 xb ee ff ii 3 1 16 bit
+ 18 0C hh ll hh ll 0 0
+ 18 09 xb hh ll 1 -1
+ 18 0D xb hh ll 0 0
+ 18 0A xb xb 0 0
+
+ movw 18 03 jj kk hh ll 0 0
+ 18 00 xb jj kk 1 -1
+ 18 04 hh ll hh ll 0 0
+ 18 01 xb hh ll 1 -1
+ 18 05 xb hh ll 0 0
+ 18 02 xb xb 0 0
+
+ After the source operand is read, the position 'pos' is incremented
+ this explains the negative offset for destination.
+
+ movb/movw above are the only instructions with this matching
+ format. */
offset = ((format & M6812_OP_IDX_P2)
- && (format & (M6811_OP_IMM8 | M6811_OP_IMM16 |
- M6811_OP_IND16)));
+ && (format & (M6811_OP_IMM8 | M6811_OP_IMM16 |
+ M6811_OP_IND16)));
+
+ if (offset)
+ {
+ /* Check xb to see position of data. */
+ status = read_memory (memaddr + pos, &buffer[0], 1, info);
+ if (status != 0)
+ {
+ return status;
+ }
+
+ if (((buffer[0] & 0xe0) == 0xe0) && ((buffer[0] & 0x04) == 0))
+ {
+ /* 9 or 16 bit. */
+ if ((buffer[0] & 0x02) == 0)
+ {
+ /* 9 bit. */
+ offset = 2;
+ }
+ else
+ {
+ /* 16 bit. */
+ offset = 3;
+ }
+ }
+ }
/* Operand with one more byte: - immediate, offset,
- direct-low address. */
+ direct-low address. */
if (format &
(M6811_OP_IMM8 | M6811_OP_IX | M6811_OP_IY | M6811_OP_DIRECT))
{
status = read_memory (memaddr + pos + offset, &buffer[0], 1, info);
if (status != 0)
+ return status;
+
+ /* This movb/movw is special (see above). */
+ if (offset < 2)
{
- return status;
+ offset = -offset;
+ pc_dst_offset = 2;
+ }
+ else
+ {
+ offset = -1;
+ pc_dst_offset = 5;
}
-
pos++;
- /* This movb/movw is special (see above). */
- offset = -offset;
-
- pc_dst_offset = 2;
if (format & M6811_OP_IMM8)
{
- (*info->fprintf_func) (info->stream, "#%d", (int) buffer[0]);
+ (*info->fprintf_func) (info->stream, "#0x%x", (int) buffer[0]);
format &= ~M6811_OP_IMM8;
- /* Set PC destination offset. */
- pc_dst_offset = 1;
+ /* Set PC destination offset. */
+ pc_dst_offset = 1;
}
else if (format & M6811_OP_IX)
{
/* Offsets are in range 0..255, print them unsigned. */
- (*info->fprintf_func) (info->stream, "%u,x", buffer[0] & 0x0FF);
+ (*info->fprintf_func) (info->stream, "0x%x,x", buffer[0] & 0x0FF);
format &= ~M6811_OP_IX;
}
else if (format & M6811_OP_IY)
{
- (*info->fprintf_func) (info->stream, "%u,y", buffer[0] & 0x0FF);
+ (*info->fprintf_func) (info->stream, "0x%x,y", buffer[0] & 0x0FF);
format &= ~M6811_OP_IY;
}
else if (format & M6811_OP_DIRECT)
{
(*info->fprintf_func) (info->stream, "*");
+ if (info->symtab_size > 0) /* Avoid duplicate 0x. */
+ (*info->fprintf_func) (info->stream, "0x");
(*info->print_address_func) (buffer[0] & 0x0FF, info);
format &= ~M6811_OP_DIRECT;
}
@@ -470,27 +609,26 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
/* Analyze the 68HC12 indexed byte. */
if (format & M6812_INDEXED_FLAGS)
{
- int indirect;
- bfd_vma endaddr;
-
- endaddr = memaddr + pos + 1;
- if (format & M6811_OP_IND16)
- endaddr += 2;
- pc_src_offset = -1;
- pc_dst_offset = 1;
+ int indirect;
+ bfd_vma endaddr;
+
+ endaddr = memaddr + pos + 1;
+ if (format & M6811_OP_IND16)
+ endaddr += 2;
+ pc_src_offset = -1;
+ pc_dst_offset = 1;
status = print_indexed_operand (memaddr + pos, info, &indirect,
- (format & M6812_DST_MOVE),
- pc_src_offset, endaddr);
+ (format & M6812_DST_MOVE),
+ pc_src_offset, endaddr, arch);
if (status < 0)
- {
- return status;
- }
+ return status;
+
pos += status;
- /* The indirect addressing mode of the call instruction does
- not need the page code. */
- if ((format & M6812_OP_PAGE) && indirect)
- format &= ~M6812_OP_PAGE;
+ /* The indirect addressing mode of the call instruction does
+ not need the page code. */
+ if ((format & M6812_OP_PAGE) && indirect)
+ format &= ~M6812_OP_PAGE;
}
/* 68HC12 dbcc/ibcc/tbcc operands. */
@@ -498,9 +636,8 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
{
status = read_memory (memaddr + pos, &buffer[0], 2, info);
if (status != 0)
- {
- return status;
- }
+ return status;
+
(*info->fprintf_func) (info->stream, "%s,",
reg_src_table[buffer[0] & 0x07]);
sval = buffer[1] & 0x0ff;
@@ -508,6 +645,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
sval |= 0xff00;
pos += 2;
+ (*info->fprintf_func) (info->stream, "0x");
(*info->print_address_func) (memaddr + pos + sval, info);
format &= ~(M6812_OP_REG | M6811_OP_JUMP_REL);
}
@@ -515,9 +653,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
{
status = read_memory (memaddr + pos, &buffer[0], 1, info);
if (status != 0)
- {
- return status;
- }
+ return status;
pos++;
(*info->fprintf_func) (info->stream, "%s,%s",
@@ -528,14 +664,13 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
if (format & (M6811_OP_IMM16 | M6811_OP_IND16))
{
int val;
- bfd_vma addr;
- unsigned page = 0;
+ bfd_vma addr;
+ unsigned page = 0;
status = read_memory (memaddr + pos + offset, &buffer[0], 2, info);
if (status != 0)
- {
- return status;
- }
+ return status;
+
if (format & M6812_OP_IDX_P2)
offset = -2;
else
@@ -544,64 +679,71 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
val = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
val &= 0x0FFFF;
- addr = val;
- pc_dst_offset = 2;
- if (format & M6812_OP_PAGE)
- {
- status = read_memory (memaddr + pos + offset, buffer, 1, info);
- if (status != 0)
- return status;
-
- page = (unsigned) buffer[0];
- if (addr >= M68HC12_BANK_BASE && addr < 0x0c000)
- addr = ((val - M68HC12_BANK_BASE)
- | (page << M68HC12_BANK_SHIFT))
- + M68HC12_BANK_VIRT;
- }
- else if ((arch & cpu6812)
- && addr >= M68HC12_BANK_BASE && addr < 0x0c000)
- {
- int cur_page;
- bfd_vma vaddr;
+ addr = val;
+ pc_dst_offset = 2;
+ if (format & M6812_OP_PAGE)
+ {
+ status = read_memory (memaddr + pos + offset, buffer, 1, info);
+ if (status != 0)
+ return status;
+
+ page = (unsigned) buffer[0];
+ if (addr >= M68HC12_BANK_BASE && addr < 0x0c000)
+ addr = ((val - M68HC12_BANK_BASE)
+ | (page << M68HC12_BANK_SHIFT))
+ + M68HC12_BANK_VIRT;
+ }
+ else if ((arch & cpu6812)
+ && addr >= M68HC12_BANK_BASE && addr < 0x0c000)
+ {
+ int cur_page;
+ bfd_vma vaddr;
- if (memaddr >= M68HC12_BANK_VIRT)
- cur_page = ((memaddr - M68HC12_BANK_VIRT)
- >> M68HC12_BANK_SHIFT);
- else
- cur_page = 0;
-
- vaddr = ((addr - M68HC12_BANK_BASE)
- + (cur_page << M68HC12_BANK_SHIFT))
- + M68HC12_BANK_VIRT;
- if (!info->symbol_at_address_func (addr, info)
- && info->symbol_at_address_func (vaddr, info))
- addr = vaddr;
- }
+ if (memaddr >= M68HC12_BANK_VIRT)
+ cur_page = ((memaddr - M68HC12_BANK_VIRT)
+ >> M68HC12_BANK_SHIFT);
+ else
+ cur_page = 0;
+
+ vaddr = ((addr - M68HC12_BANK_BASE)
+ + (cur_page << M68HC12_BANK_SHIFT))
+ + M68HC12_BANK_VIRT;
+ if (!info->symbol_at_address_func (addr, info)
+ && info->symbol_at_address_func (vaddr, info))
+ addr = vaddr;
+ }
if (format & M6811_OP_IMM16)
{
format &= ~M6811_OP_IMM16;
(*info->fprintf_func) (info->stream, "#");
}
else
- format &= ~M6811_OP_IND16;
+ {
+ format &= ~M6811_OP_IND16;
+ }
+
+ if (info->symtab_size > 0) /* Avoid duplicate 0x from core binutils. */
+ (*info->fprintf_func) (info->stream, "0x");
(*info->print_address_func) (addr, info);
- if (format & M6812_OP_PAGE)
- {
- (* info->fprintf_func) (info->stream, " {");
- (* info->print_address_func) (val, info);
- (* info->fprintf_func) (info->stream, ", %d}", page);
- format &= ~M6812_OP_PAGE;
- pos += 1;
- }
+ if (format & M6812_OP_PAGE)
+ {
+ (* info->fprintf_func) (info->stream, " {");
+ if (info->symtab_size > 0) /* Avoid duplicate 0x from core binutils. */
+ (*info->fprintf_func) (info->stream, "0x");
+ (* info->print_address_func) (val, info);
+ (* info->fprintf_func) (info->stream, ", 0x%x}", page);
+ format &= ~M6812_OP_PAGE;
+ pos += 1;
+ }
}
if (format & M6812_OP_IDX_P2)
{
(*info->fprintf_func) (info->stream, ", ");
status = print_indexed_operand (memaddr + pos + offset, info,
- 0, 1, pc_dst_offset,
- memaddr + pos + offset + 1);
+ 0, 1, pc_dst_offset,
+ memaddr + pos + offset + 1, arch);
if (status < 0)
return status;
pos += status;
@@ -615,30 +757,30 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
status = read_memory (memaddr + pos + offset, &buffer[0], 2, info);
if (status != 0)
- {
- return status;
- }
+ return status;
+
pos += 2;
val = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
val &= 0x0FFFF;
+ if (info->symtab_size > 0) /* Avoid duplicate 0x from core binutils. */
+ (*info->fprintf_func) (info->stream, "0x");
(*info->print_address_func) (val, info);
}
/* M6811_OP_BITMASK and M6811_OP_JUMP_REL must be treated separately
- and in that order. The brset/brclr insn have a bitmask and then
- a relative branch offset. */
+ and in that order. The brset/brclr insn have a bitmask and then
+ a relative branch offset. */
if (format & M6811_OP_BITMASK)
{
status = read_memory (memaddr + pos, &buffer[0], 1, info);
if (status != 0)
- {
- return status;
- }
+ return status;
+
pos++;
- (*info->fprintf_func) (info->stream, " #$%02x%s",
+ (*info->fprintf_func) (info->stream, ", #0x%02x%s",
buffer[0] & 0x0FF,
- (format & M6811_OP_JUMP_REL ? " " : ""));
+ (format & M6811_OP_JUMP_REL ? ", " : ""));
format &= ~M6811_OP_BITMASK;
}
if (format & M6811_OP_JUMP_REL)
@@ -647,10 +789,9 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
status = read_memory (memaddr + pos, &buffer[0], 1, info);
if (status != 0)
- {
- return status;
- }
+ return status;
+ (*info->fprintf_func) (info->stream, "0x");
pos++;
val = (buffer[0] & 0x80) ? buffer[0] | 0xFFFFFF00 : buffer[0];
(*info->print_address_func) (memaddr + pos + val, info);
@@ -662,15 +803,14 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
status = read_memory (memaddr + pos, &buffer[0], 2, info);
if (status != 0)
- {
- return status;
- }
+ return status;
pos += 2;
val = ((buffer[0] << 8) | (buffer[1] & 0x0FF));
if (val & 0x8000)
val |= 0xffff0000;
+ (*info->fprintf_func) (info->stream, "0x");
(*info->print_address_func) (memaddr + pos + val, info);
format &= ~M6812_OP_JUMP_REL16;
}
@@ -681,28 +821,24 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
status = read_memory (memaddr + pos + offset, &buffer[0], 1, info);
if (status != 0)
- {
- return status;
- }
+ return status;
+
pos += 1;
val = buffer[0] & 0x0ff;
- (*info->fprintf_func) (info->stream, ", %d", val);
+ (*info->fprintf_func) (info->stream, ", 0x%x", val);
}
#ifdef DEBUG
/* Consistency check. 'format' must be 0, so that we have handled
- all formats; and the computed size of the insn must match the
- opcode table content. */
+ all formats; and the computed size of the insn must match the
+ opcode table content. */
if (format & ~(M6811_OP_PAGE4 | M6811_OP_PAGE3 | M6811_OP_PAGE2))
- {
- (*info->fprintf_func) (info->stream, "; Error, format: %lx", format);
- }
+ (*info->fprintf_func) (info->stream, "; Error, format: %lx", format);
+
if (pos != opcode->size)
- {
- (*info->fprintf_func) (info->stream, "; Error, size: %ld expect %d",
- pos, opcode->size);
- }
+ (*info->fprintf_func) (info->stream, "; Error, size: %ld expect %d",
+ pos, opcode->size);
#endif
return pos;
}
@@ -710,7 +846,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
/* Opcode not recognized. */
if (format == M6811_OP_PAGE2 && arch & cpu6812
&& ((code >= 0x30 && code <= 0x39) || (code >= 0x40)))
- (*info->fprintf_func) (info->stream, "trap\t#%d", code & 0x0ff);
+ (*info->fprintf_func) (info->stream, "trap\t#0x%02x", code & 0x0ff);
else if (format == M6811_OP_PAGE2)
(*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x",
@@ -740,3 +876,15 @@ print_insn_m68hc12 (bfd_vma memaddr, struct disassemble_info* info)
{
return print_insn (memaddr, info, cpu6812);
}
+
+int
+print_insn_m9s12x (bfd_vma memaddr, struct disassemble_info* info)
+{
+ return print_insn (memaddr, info, cpu6812|cpu9s12x);
+}
+
+int
+print_insn_m9s12xg (bfd_vma memaddr, struct disassemble_info* info)
+{
+ return print_insn (memaddr, info, cpuxgate);
+}
diff --git a/opcodes/m68hc11-opc.c b/opcodes/m68hc11-opc.c
index ac6259d..79c1d27 100644
--- a/opcodes/m68hc11-opc.c
+++ b/opcodes/m68hc11-opc.c
@@ -1,6 +1,9 @@
-/* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list
- Copyright 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc.
+/* m68hc11-opc.c -- Motorola 68HC11, 68HC12, 9S12X and XGATE opcode list
+ Copyright 1999, 2000, 2002, 2005, 2007, 2012
+ Free Software Foundation, Inc.
Written by Stephane Carrez (stcarrez@nerim.fr)
+ XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk)
+ Note: min/max cycles not updated for S12X opcodes.
This file is part of the GNU opcodes library.
@@ -103,956 +106,1611 @@
#define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER)
/*
- { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 },
- +-- cpu
+ { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811, 0 },
+ +-- cpu +-- XGATE opcode mask
Name -+ +------- Insn CCR changes
Format ------+ +----------- Max # cycles
Size --------------------+ +--------------- Min # cycles
+--------------------- Opcode
*/
const struct m68hc11_opcode m68hc11_opcodes[] = {
- { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811 },
- { "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812 },
- { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811 },
- { "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811 },
-
- { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
- { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
- { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
- { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811 },
- { "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811 },
- { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812 },
- { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812 },
- { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812 },
- { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812 },
- { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812 },
-
- { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
- { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
- { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
- { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811 },
- { "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811 },
- { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812 },
- { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812 },
- { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812 },
- { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812 },
- { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812 },
-
- { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
- { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
- { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
- { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811 },
- { "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811 },
- { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812 },
- { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812 },
- { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812 },
- { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812 },
- { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812 },
-
- { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812 },
- { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
- { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 },
- { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811 },
- { "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811 },
- { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812 },
- { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812 },
- { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812 },
- { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812 },
- { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812 },
-
- { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812 },
- { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811 },
- { "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811 },
- { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812 },
- { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812 },
- { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812 },
- { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812 },
- { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812 },
-
- { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812 },
-
- { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
- { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 },
- { "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 },
- { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 },
- { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 },
- { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 },
- { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 },
- { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 },
-
- { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 },
- { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 },
-
- { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
- { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811 },
- { "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811 },
- { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812 },
- { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812 },
- { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812 },
- { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812 },
- { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812 },
-
- { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
-
- { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812 },
-
- { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811 },
- { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811},
- { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
-
- { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812 },
-
- { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
+ { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811, 0 },
+ { "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811, 0 },
+ { "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811, 0 },
+
+ { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811, 0 },
+ { "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811, 0 },
+ { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+
+ { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811, 0 },
+ { "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811, 0 },
+ { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+
+ { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811, 0 },
+ { "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811, 0 },
+ { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+
+ { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811, 0 },
+ { "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811, 0 },
+ { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+
+ { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "addx", OP_IMM16 | OP_PAGE2, 3, 0x8b, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "addx", OP_DIRECT | OP_PAGE2, 2, 0x9b, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "addx", OP_IND16 | OP_PAGE2, 3, 0xbb, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "addx", OP_IDX | OP_PAGE2, 2, 0xab, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "addx", OP_IDX_1 | OP_PAGE2, 3, 0xab, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "addx", OP_IDX_2 | OP_PAGE2, 4, 0xab, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "addx", OP_D_IDX | OP_PAGE2, 2, 0xab, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "addx", OP_D_IDX_2 | OP_PAGE2, 4, 0xab, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "addy", OP_IMM16 | OP_PAGE2, 3, 0xcb, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "addy", OP_DIRECT | OP_PAGE2, 2, 0xdb, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "addy", OP_IND16 | OP_PAGE2, 3, 0xfb, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "addy", OP_IDX | OP_PAGE2, 2, 0xeb, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "addy", OP_IDX_1 | OP_PAGE2, 3, 0xeb, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "addy", OP_IDX_2 | OP_PAGE2, 4, 0xeb, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "addy", OP_D_IDX | OP_PAGE2, 2, 0xeb, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "addy", OP_D_IDX_2 | OP_PAGE2, 4, 0xeb, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "aded", OP_IMM16 | OP_PAGE2, 3, 0xc3, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "aded", OP_DIRECT | OP_PAGE2, 2, 0xd3, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "aded", OP_IND16 | OP_PAGE2, 3, 0xf3, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "aded", OP_IDX | OP_PAGE2, 2, 0xe3, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "aded", OP_IDX_1 | OP_PAGE2, 3, 0xe3, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "aded", OP_IDX_2 | OP_PAGE2, 4, 0xe3, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "aded", OP_D_IDX | OP_PAGE2, 2, 0xe3, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "aded", OP_D_IDX_2 | OP_PAGE2, 4, 0xe3, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "adex", OP_IMM16 | OP_PAGE2, 3, 0x89, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "adex", OP_DIRECT | OP_PAGE2, 2, 0x99, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "adex", OP_IND16 | OP_PAGE2, 3, 0xb9, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "adex", OP_IDX | OP_PAGE2, 2, 0xa9, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "adex", OP_IDX_1 | OP_PAGE2, 3, 0xa9, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "adex", OP_IDX_2 | OP_PAGE2, 4, 0xa9, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "adex", OP_D_IDX | OP_PAGE2, 2, 0xa9, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "adex", OP_D_IDX_2 | OP_PAGE2, 4, 0xa9, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "adey", OP_IMM16 | OP_PAGE2, 3, 0xc9, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "adey", OP_DIRECT | OP_PAGE2, 2, 0xd9, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "adey", OP_IND16 | OP_PAGE2, 3, 0xf9, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "adey", OP_IDX | OP_PAGE2, 2, 0xe9, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "adey", OP_IDX_1 | OP_PAGE2, 3, 0xe9, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "adey", OP_IDX_2 | OP_PAGE2, 4, 0xe9, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "adey", OP_D_IDX | OP_PAGE2, 2, 0xe9, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "adey", OP_D_IDX_2 | OP_PAGE2, 4, 0xe9, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812|cpu9s12x, 0 },
+
+ { "andx", OP_IMM16 | OP_PAGE2, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andx", OP_DIRECT | OP_PAGE2, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andx", OP_IND16 | OP_PAGE2, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andx", OP_IDX | OP_PAGE2, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andx", OP_IDX_1 | OP_PAGE2, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andx", OP_IDX_2 | OP_PAGE2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andx", OP_D_IDX | OP_PAGE2, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andx", OP_D_IDX_2 | OP_PAGE2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "andy", OP_IMM16 | OP_PAGE2, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andy", OP_DIRECT | OP_PAGE2, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andy", OP_IND16 | OP_PAGE2, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andy", OP_IDX | OP_PAGE2, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andy", OP_IDX_1 | OP_PAGE2, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andy", OP_IDX_2 | OP_PAGE2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andy", OP_D_IDX | OP_PAGE2, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "andy", OP_D_IDX_2 | OP_PAGE2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811, 0 },
+ { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "aslw", OP_IND16 | OP_PAGE2, 3, 0x78, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "aslw", OP_IDX | OP_PAGE2, 2, 0x68, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "aslw", OP_IDX_1 | OP_PAGE2, 3, 0x68, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "aslw", OP_IDX_2 | OP_PAGE2, 4, 0x68, 5, 5, CHG_NZVC, cpu9s12x, 0 },
+ { "aslw", OP_D_IDX | OP_PAGE2, 2, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "aslw", OP_D_IDX_2 | OP_PAGE2, 4, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "aslx", OP_NONE | OP_PAGE2, 1, 0x48, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "asly", OP_NONE | OP_PAGE2, 1, 0x58, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+
+ { "asrw", OP_IND16 | OP_PAGE2, 3, 0x77, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "asrw", OP_IDX | OP_PAGE2, 2, 0x67, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "asrw", OP_IDX_1 | OP_PAGE2, 3, 0x67, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "asrw", OP_IDX_2 | OP_PAGE2, 4, 0x67, 5, 5, CHG_NZVC, cpu9s12x, 0 },
+ { "asrw", OP_D_IDX | OP_PAGE2, 2, 0x67, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "asrw", OP_D_IDX_2 | OP_PAGE2, 4, 0x67, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "asrx", OP_NONE | OP_PAGE2, 1, 0x47, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "asry", OP_NONE | OP_PAGE2, 1, 0x57, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
+
+ { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+
+ { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+
+ { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
- { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
+ { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "bitx", OP_IMM16 | OP_PAGE2, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bitx", OP_DIRECT | OP_PAGE2, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bitx", OP_IND16 | OP_PAGE2, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bitx", OP_IDX | OP_PAGE2, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bitx", OP_IDX_1 | OP_PAGE2, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bitx", OP_IDX_2 | OP_PAGE2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bitx", OP_D_IDX | OP_PAGE2, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bitx", OP_D_IDX_2 | OP_PAGE2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "bity", OP_IMM16 | OP_PAGE2, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bity", OP_DIRECT | OP_PAGE2, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bity", OP_IND16 | OP_PAGE2, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bity", OP_IDX | OP_PAGE2, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bity", OP_IDX_1 | OP_PAGE2, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bity", OP_IDX_2 | OP_PAGE2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bity", OP_D_IDX | OP_PAGE2, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "bity", OP_D_IDX_2 | OP_PAGE2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
{ "brclr", OP_BITMASK | OP_JUMP_REL
- | OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811 },
+ | OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811, 0 },
{ "brclr", OP_BITMASK | OP_JUMP_REL
- | OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811 },
+ | OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811, 0 },
{ "brclr", OP_BITMASK | OP_JUMP_REL
- | OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811 },
+ | OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811, 0 },
{ "brclr", OP_BITMASK | OP_JUMP_REL
- | OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812 },
+ | OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "brclr", OP_BITMASK | OP_JUMP_REL
- | OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812 },
+ | OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "brclr", OP_BITMASK | OP_JUMP_REL
- | OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812 },
+ | OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "brclr", OP_BITMASK | OP_JUMP_REL
- | OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812 },
+ | OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "brclr", OP_BITMASK
| OP_JUMP_REL
- | OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812 },
+ | OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 },
- { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812 },
+ { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
{ "brset", OP_BITMASK | OP_JUMP_REL
- | OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811 },
+ | OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811, 0 },
{ "brset", OP_BITMASK
| OP_JUMP_REL
- | OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811 },
+ | OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811, 0 },
{ "brset", OP_BITMASK | OP_JUMP_REL
- | OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811 },
+ | OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811, 0 },
{ "brset", OP_BITMASK | OP_JUMP_REL
- | OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812 },
+ | OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "brset", OP_BITMASK | OP_JUMP_REL
- | OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812 },
+ | OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "brset", OP_BITMASK | OP_JUMP_REL
- | OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812 },
+ | OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "brset", OP_BITMASK | OP_JUMP_REL
- | OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812 },
+ | OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "brset", OP_BITMASK | OP_JUMP_REL
- | OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812 },
+ | OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 },
- { "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811 },
- { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 },
- { "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812 },
+ { "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
- { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811 },
- { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812 },
+ { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811, 0 },
+ { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
- { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
- { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812 },
+ { "btas", OP_BITMASK|OP_DIRECT | OP_PAGE2, 3, 0x35, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "btas", OP_BITMASK|OP_IND16 | OP_PAGE2, 4, 0x36, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "btas", OP_BITMASK|OP_IDX | OP_PAGE2, 3, 0x37, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "btas", OP_BITMASK|OP_IDX_1 | OP_PAGE2, 4, 0x37, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "btas", OP_BITMASK|OP_IDX_2 | OP_PAGE2, 5, 0x37, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
+ { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
{ "call", OP_IND16 | OP_PAGE
- | OP_BRANCH, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 },
+ | OP_BRANCH, 4, 0x4a, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "call", OP_IDX | OP_PAGE
- | OP_BRANCH, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 },
+ | OP_BRANCH, 3, 0x4b, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "call", OP_IDX_1 | OP_PAGE
- | OP_BRANCH, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 },
+ | OP_BRANCH, 4, 0x4b, 8, 8, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "call", OP_IDX_2 | OP_PAGE
- | OP_BRANCH, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 },
+ | OP_BRANCH, 5, 0x4b, 9, 9, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "call", OP_D_IDX
- | OP_BRANCH, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 },
+ | OP_BRANCH, 2, 0x4b, 10, 10, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "call", OP_D_IDX_2
- | OP_BRANCH, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 },
-
- { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 },
- { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 },
-
- { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811 },
- { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811 },
-
- { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 },
- { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 },
- { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 },
- { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 },
- { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 },
- { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 },
- { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 },
- { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },
- { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },
-
- { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 },
- { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 },
- { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 },
- { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 },
-
- { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811 },
-
- { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811 },
- { "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811 },
- { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812 },
- { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812 },
- { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812 },
- { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812 },
- { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812 },
-
- { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811 },
- { "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811 },
- { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812 },
- { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812 },
- { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812 },
- { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812 },
- { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812 },
-
- { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 },
- { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 },
- { "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811 },
- { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 },
- { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812 },
- { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 },
- { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812 },
- { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 },
- { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 },
-
- { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 },
- { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 },
- { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 },
- { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 },
-
- { "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811 },
- { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811 },
- { "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811 },
- { "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },
- { "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },
- { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812 },
- { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812 },
- { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812 },
- { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812 },
- { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812 },
- { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812 },
- { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812 },
- { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812 },
-
- { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812 },
- { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812 },
- { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812 },
- { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812 },
- { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812 },
- { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812 },
- { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812 },
- { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812 },
-
- { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811 },
- { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811 },
- { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811 },
- { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811 },
- { "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },
- { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812 },
- { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812 },
- { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812 },
- { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812 },
- { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812 },
- { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812 },
- { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812 },
- { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812 },
-
- { "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811 },
- { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811 },
- { "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },
- { "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811 },
- { "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },
- { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812 },
- { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812 },
- { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812 },
- { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812 },
- { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812 },
- { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812 },
- { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812 },
- { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812 },
+ | OP_BRANCH, 4, 0x4b, 10, 10, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811, 0 },
+ { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811, 0 },
+ { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811, 0 },
+
+ { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811, 0 },
+ { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811, 0 },
+ { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811, 0 },
+ { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
+ { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
+ { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
+ { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
+ { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
+ { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
+
+ { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811, 0 },
+ { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811, 0 },
+ { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
+ { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
+
+ { "clrw", OP_IND16 | OP_PAGE2, 3, 0x79, 4, 4, SET_Z_CLR_NVC, cpu9s12x, 0 },
+ { "clrw", OP_IDX | OP_PAGE2, 2, 0x69, 3, 3, SET_Z_CLR_NVC, cpu9s12x, 0 },
+ { "clrw", OP_IDX_1 | OP_PAGE2, 3, 0x69, 4, 4, SET_Z_CLR_NVC, cpu9s12x, 0 },
+ { "clrw", OP_IDX_2 | OP_PAGE2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu9s12x, 0 },
+ { "clrw", OP_D_IDX | OP_PAGE2, 2, 0x69, 6, 6, SET_Z_CLR_NVC, cpu9s12x, 0 },
+ { "clrw", OP_D_IDX_2 | OP_PAGE2, 4, 0x69, 6, 6, SET_Z_CLR_NVC, cpu9s12x, 0 },
+
+ { "clrx", OP_NONE | OP_PAGE2, 3, 0x87, 4, 4, SET_Z_CLR_NVC, cpu9s12x, 0 },
+
+ { "clry", OP_NONE | OP_PAGE2, 3, 0xc7, 4, 4, SET_Z_CLR_NVC, cpu9s12x, 0 },
+
+ { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811, 0 },
+
+ { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811, 0 },
+ { "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811, 0 },
+ { "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
+ { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
+ { "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
+ { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
+ { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
+ { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "comw", OP_IND16 | OP_PAGE2, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "comw", OP_IDX | OP_PAGE2, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "comw", OP_IDX_1 | OP_PAGE2, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "comw", OP_IDX_2 | OP_PAGE2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "comw", OP_D_IDX | OP_PAGE2, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "comw", OP_D_IDX_2 | OP_PAGE2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "comx", OP_NONE | OP_PAGE2, 1, 0x41, 2, 2, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "comy", OP_NONE | OP_PAGE2, 1, 0x51, 2, 2, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "cped", OP_IMM16 | OP_PAGE2, 3, 0x8c, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "cped", OP_DIRECT | OP_PAGE2, 2, 0x9c, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cped", OP_IND16 | OP_PAGE2, 3, 0xbc, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cped", OP_IDX | OP_PAGE2, 2, 0xac, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cped", OP_IDX_1 | OP_PAGE2, 3, 0xac, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cped", OP_IDX_2 | OP_PAGE2, 4, 0xac, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "cped", OP_D_IDX | OP_PAGE2, 2, 0xac, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "cped", OP_D_IDX_2 | OP_PAGE2, 4, 0xac, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "cpes", OP_IMM16 | OP_PAGE2, 3, 0x8f, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "cpes", OP_DIRECT | OP_PAGE2, 2, 0x9f, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpes", OP_IND16 | OP_PAGE2, 3, 0xbf, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpes", OP_IDX | OP_PAGE2, 2, 0xaf, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpes", OP_IDX_1 | OP_PAGE2, 3, 0xaf, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpes", OP_IDX_2 | OP_PAGE2, 4, 0xaf, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "cpes", OP_D_IDX | OP_PAGE2, 2, 0xaf, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "cpes", OP_D_IDX_2 | OP_PAGE2, 4, 0xaf, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "cpex", OP_IMM16 | OP_PAGE2, 3, 0x8e, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "cpex", OP_DIRECT | OP_PAGE2, 2, 0x9e, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpex", OP_IND16 | OP_PAGE2, 3, 0xbe, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpex", OP_IDX | OP_PAGE2, 2, 0xae, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpex", OP_IDX_1 | OP_PAGE2, 3, 0xae, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpex", OP_IDX_2 | OP_PAGE2, 4, 0xae, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "cpex", OP_D_IDX | OP_PAGE2, 2, 0xae, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "cpex", OP_D_IDX_2 | OP_PAGE2, 4, 0xae, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "cpey", OP_IMM16 | OP_PAGE2, 3, 0x8d, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "cpey", OP_DIRECT | OP_PAGE2, 2, 0x9d, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpey", OP_IND16 | OP_PAGE2, 3, 0xbd, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpey", OP_IDX | OP_PAGE2, 2, 0xad, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpey", OP_IDX_1 | OP_PAGE2, 3, 0xad, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "cpey", OP_IDX_2 | OP_PAGE2, 4, 0xad, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "cpey", OP_D_IDX | OP_PAGE2, 2, 0xad, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "cpey", OP_D_IDX_2 | OP_PAGE2, 4, 0xad, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811, 0 },
+ { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
/* After 'daa', the Z flag is undefined. Mark it as changed. */
- { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811 },
- { "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812 },
+ { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811, 0 },
+ { "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
{ "dbeq", OP_DBEQ_MARKER
- | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 },
+ | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "dbne", OP_DBNE_MARKER
- | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 },
-
- { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811 },
- { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811 },
- { "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811 },
- { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812 },
- { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812 },
- { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812 },
- { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812 },
- { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812 },
- { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812 },
-
- { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811 },
-
- { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811 },
- { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812 },
- { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811 },
- { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812 },
-
- { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu6811 },
- { "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811 },
- { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812 },
-
- { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812 },
- { "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812 },
- { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812 },
-
- { "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812 },
- { "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812 },
- { "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812 },
- { "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812 },
- { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812 },
-
- { "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812 },
- { "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812 },
- { "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812 },
- { "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812 },
- { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812 },
-
- { "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812 },
- { "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812 },
- { "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812 },
- { "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812 },
- { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812 },
-
- { "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812 },
- { "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812 },
- { "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812 },
- { "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812 },
- { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812 },
-
- { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812 },
- { "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812 },
-
- { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812 },
-
+ | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811, 0 },
+ { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811, 0 },
+ { "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811, 0 },
+ { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812|cpu9s12x, 0 },
+
+ { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811, 0 },
+
+ { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811, 0 },
+ { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811, 0 },
+ { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812|cpu9s12x, 0 },
+
+ { "decw", OP_IND16 | OP_PAGE2, 3, 0x73, 4, 4, CHG_NZV, cpu9s12x, 0 },
+ { "decw", OP_IDX | OP_PAGE2, 2, 0x63, 3, 3, CHG_NZV, cpu9s12x, 0 },
+ { "decw", OP_IDX_1 | OP_PAGE2, 3, 0x63, 4, 4, CHG_NZV, cpu9s12x, 0 },
+ { "decw", OP_IDX_2 | OP_PAGE2, 4, 0x63, 5, 5, CHG_NZV, cpu9s12x, 0 },
+ { "decw", OP_D_IDX | OP_PAGE2, 2, 0x63, 6, 6, CHG_NZV, cpu9s12x, 0 },
+ { "decw", OP_D_IDX_2 | OP_PAGE2, 4, 0x63, 6, 6, CHG_NZV, cpu9s12x, 0 },
+
+ { "decx", OP_NONE | OP_PAGE2, 3, 0x43, 4, 4, CHG_NZV, cpu9s12x, 0 },
+
+ { "decy", OP_NONE | OP_PAGE2, 3, 0x53, 4, 4, CHG_NZV, cpu9s12x, 0 },
+
+ { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu9s12x|cpu6811, 0 },
+ { "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811, 0 },
+ { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812|cpu9s12x, 0 },
+
+ { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812|cpu9s12x, 0 },
+ { "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812|cpu9s12x, 0 },
+
+ { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "eorx", OP_IMM16 | OP_PAGE2, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eorx", OP_DIRECT | OP_PAGE2, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eorx", OP_IND16 | OP_PAGE2, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eorx", OP_IDX | OP_PAGE2, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eorx", OP_IDX_1 | OP_PAGE2, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eorx", OP_IDX_2 | OP_PAGE2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eorx", OP_D_IDX | OP_PAGE2, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eorx", OP_D_IDX_2 | OP_PAGE2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "eory", OP_IMM16 | OP_PAGE2, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eory", OP_DIRECT | OP_PAGE2, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eory", OP_IND16 | OP_PAGE2, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eory", OP_IDX | OP_PAGE2, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eory", OP_IDX_1 | OP_PAGE2, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eory", OP_IDX_2 | OP_PAGE2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eory", OP_D_IDX | OP_PAGE2, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "eory", OP_D_IDX_2 | OP_PAGE2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812|cpu9s12x, 0 },
+
+/* S12X has more exg variants, most are pointless so not supported */
{ "exg", OP_EXG_MARKER
- | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },
-
- { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811},
- { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812 },
+ | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811, 0 },
+ { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812|cpu9s12x, 0 },
+
+ { "gldaa", OP_DIRECT | OP_PAGE2, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldaa", OP_IND16 | OP_PAGE2, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldaa", OP_IDX | OP_PAGE2, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldaa", OP_IDX_1 | OP_PAGE2, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldaa", OP_IDX_2 | OP_PAGE2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldaa", OP_D_IDX | OP_PAGE2, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldaa", OP_D_IDX_2 | OP_PAGE2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gldab", OP_DIRECT | OP_PAGE2, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldab", OP_IND16 | OP_PAGE2, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldab", OP_IDX | OP_PAGE2, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldab", OP_IDX_1 | OP_PAGE2, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldab", OP_IDX_2 | OP_PAGE2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldab", OP_D_IDX | OP_PAGE2, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldab", OP_D_IDX_2 | OP_PAGE2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gldd", OP_DIRECT | OP_PAGE2, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldd", OP_IND16 | OP_PAGE2, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldd", OP_IDX | OP_PAGE2, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldd", OP_IDX_1 | OP_PAGE2, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldd", OP_IDX_2 | OP_PAGE2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldd", OP_D_IDX | OP_PAGE2, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldd", OP_D_IDX_2 | OP_PAGE2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "glds", OP_DIRECT | OP_PAGE2, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "glds", OP_IND16 | OP_PAGE2, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "glds", OP_IDX | OP_PAGE2, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "glds", OP_IDX_1 | OP_PAGE2, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "glds", OP_IDX_2 | OP_PAGE2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "glds", OP_D_IDX | OP_PAGE2, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "glds", OP_D_IDX_2 | OP_PAGE2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gldx", OP_DIRECT | OP_PAGE2, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldx", OP_IND16 | OP_PAGE2, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldx", OP_IDX | OP_PAGE2, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldx", OP_IDX_1 | OP_PAGE2, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldx", OP_IDX_2 | OP_PAGE2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldx", OP_D_IDX | OP_PAGE2, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldx", OP_D_IDX_2 | OP_PAGE2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gldy", OP_DIRECT | OP_PAGE2, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldy", OP_IND16 | OP_PAGE2, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldy", OP_IDX | OP_PAGE2, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldy", OP_IDX_1 | OP_PAGE2, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldy", OP_IDX_2 | OP_PAGE2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldy", OP_D_IDX | OP_PAGE2, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gldy", OP_D_IDX_2 | OP_PAGE2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gstaa", OP_DIRECT | OP_PAGE2, 2, 0x5a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstaa", OP_IND16 | OP_PAGE2, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstaa", OP_IDX | OP_PAGE2, 2, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstaa", OP_IDX_1 | OP_PAGE2, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstaa", OP_IDX_2 | OP_PAGE2, 4, 0x6a, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstaa", OP_D_IDX | OP_PAGE2, 2, 0x6a, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstaa", OP_D_IDX_2 | OP_PAGE2, 4, 0x6a, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gstab", OP_DIRECT | OP_PAGE2, 2, 0x5b, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstab", OP_IND16 | OP_PAGE2, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstab", OP_IDX | OP_PAGE2, 2, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstab", OP_IDX_1 | OP_PAGE2, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstab", OP_IDX_2 | OP_PAGE2, 4, 0x6b, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstab", OP_D_IDX | OP_PAGE2, 2, 0x6b, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstab", OP_D_IDX_2 | OP_PAGE2, 4, 0x6b, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gstd", OP_DIRECT | OP_PAGE2, 2, 0x5c, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstd", OP_IND16 | OP_PAGE2, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstd", OP_IDX | OP_PAGE2, 2, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstd", OP_IDX_1 | OP_PAGE2, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstd", OP_IDX_2 | OP_PAGE2, 4, 0x6c, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstd", OP_D_IDX | OP_PAGE2, 2, 0x6c, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstd", OP_D_IDX_2 | OP_PAGE2, 4, 0x6c, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gsts", OP_DIRECT | OP_PAGE2, 2, 0x5f, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsts", OP_IND16 | OP_PAGE2, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsts", OP_IDX | OP_PAGE2, 2, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsts", OP_IDX_1 | OP_PAGE2, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsts", OP_IDX_2 | OP_PAGE2, 4, 0x6f, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsts", OP_D_IDX | OP_PAGE2, 2, 0x6f, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsts", OP_D_IDX_2 | OP_PAGE2, 4, 0x6f, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gstx", OP_DIRECT | OP_PAGE2, 2, 0x5e, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstx", OP_IND16 | OP_PAGE2, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstx", OP_IDX | OP_PAGE2, 2, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstx", OP_IDX_1 | OP_PAGE2, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstx", OP_IDX_2 | OP_PAGE2, 4, 0x6e, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstx", OP_D_IDX | OP_PAGE2, 2, 0x6e, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gstx", OP_D_IDX_2 | OP_PAGE2, 4, 0x6e, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "gsty", OP_DIRECT | OP_PAGE2, 2, 0x5d, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsty", OP_IND16 | OP_PAGE2, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsty", OP_IDX | OP_PAGE2, 2, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsty", OP_IDX_1 | OP_PAGE2, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsty", OP_IDX_2 | OP_PAGE2, 4, 0x6d, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsty", OP_D_IDX | OP_PAGE2, 2, 0x6d, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "gsty", OP_D_IDX_2 | OP_PAGE2, 4, 0x6d, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
{ "ibeq", OP_IBEQ_MARKER
- | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
+ | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
{ "ibne", OP_IBNE_MARKER
- | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
-
- { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811},
- { "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812 },
- { "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812 },
-
- { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811 },
- { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811 },
- { "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811 },
- { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812 },
- { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812 },
- { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812 },
- { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812 },
- { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812 },
- { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812 },
-
- { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811 },
- { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812 },
- { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811 },
- { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812 },
-
- { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811 },
-
- { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812 },
- { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 },
- { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 },
-
- { "jmp", OP_IND16 | OP_BRANCH, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 },
- { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 },
- { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 },
- { "jmp", OP_IND16 | OP_BRANCH, 3, 0x06, 3, 3, CHG_NONE, cpu6812 },
- { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 },
- { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 },
- { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 },
- { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 },
- { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 },
-
- { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 },
- { "jsr", OP_IND16 | OP_BRANCH, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 },
- { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 },
- { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 },
- { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x17, 4, 4, CHG_NONE, cpu6812 },
- { "jsr", OP_IND16 | OP_BRANCH, 3, 0x16, 4, 3, CHG_NONE, cpu6812 },
- { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 },
- { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 },
- { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 },
- { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812 },
- { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812 },
-
- { "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 },
- { "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 },
- { "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812 },
- { "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812 },
- { "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812 },
- { "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812 },
- { "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 },
- { "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812 },
- { "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 },
- { "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812 },
- { "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812 },
- { "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812 },
- { "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812 },
- { "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812 },
- { "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812 },
- { "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812 },
- { "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812 },
- { "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812 },
-
- { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811 },
- { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812 },
- { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812 },
- { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812 },
-
- { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812 },
- { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812 },
- { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812 },
-
- { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812 },
- { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812 },
- { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812 },
-
- { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
- { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 },
- { "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 },
- { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 },
- { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 },
- { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 },
- { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 },
- { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 },
-
- { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 },
- { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 },
-
- { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812},
- { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811 },
- { "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811 },
- { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812 },
- { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812 },
- { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812 },
- { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 },
- { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 },
-
- { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812},
- { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812},
- { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811 },
- { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812 },
-
- { "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812 },
- { "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812 },
- { "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812 },
- { "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812 },
- { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812 },
-
- { "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812 },
- { "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812 },
- { "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812 },
- { "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812 },
- { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812 },
-
- { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812 },
-
- { "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812 },
- { "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812 },
- { "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812 },
- { "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812 },
- { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812 },
-
- { "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812 },
- { "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812 },
- { "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812 },
- { "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812 },
- { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812 },
-
- { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812 },
- { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812 },
- { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812 },
- { "movb", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812 },
- { "movb", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812 },
- { "movb", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812 },
-
- { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812 },
- { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812 },
- { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812 },
- { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812 },
- { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812 },
- { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812 },
-
- { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811 },
- { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812 },
-
- { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
- { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811 },
- { "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811 },
- { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812 },
- { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812 },
- { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812 },
- { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812 },
- { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812 },
-
- { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811 },
- { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812 },
-
- { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 },
- { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812 },
- { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 },
- { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 },
-
- { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812 },
-
- { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812 },
- { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812 },
- { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812 },
- { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812 },
- { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811 },
- { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812 },
- { "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811 },
- { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812 },
-
- { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812 },
- { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812 },
- { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812 },
- { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812 },
- { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811 },
- { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812 },
- { "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811 },
- { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812 },
-
- { "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812 },
- { "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812 },
-
- { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811 },
- { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811 },
- { "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811 },
- { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812 },
- { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812 },
- { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812 },
- { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812 },
- { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812 },
- { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812 },
-
- { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811 },
- { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812 },
- { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811 },
- { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812 },
-
- { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812 },
- { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811 },
- { "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811 },
- { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812 },
- { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812 },
- { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812 },
- { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812 },
- { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812 },
-
- { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
-
- { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812 },
- { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811},
- { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812},
- { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811 },
- { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812 },
-
- { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811 },
- { "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812 },
-
- { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811 },
- { "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811 },
- { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812 },
- { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812 },
- { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812 },
- { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812 },
- { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812 },
-
- { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811 },
- { "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811 },
- { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812 },
- { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812 },
- { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812 },
- { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812 },
- { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812 },
-
- { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811 },
- { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811 },
- { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811 },
-
+ | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811, 0 },
+ { "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812|cpu9s12x, 0 },
+ { "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811, 0 },
+ { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811, 0 },
+ { "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811, 0 },
+ { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812|cpu9s12x, 0 },
+
+ { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811, 0 },
+ { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812|cpu9s12x, 0 },
+ { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811, 0 },
+ { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812|cpu9s12x, 0 },
+
+ { "incw", OP_IND16 | OP_PAGE2, 3, 0x72, 4, 4, CHG_NZV, cpu9s12x, 0 },
+ { "incw", OP_IDX | OP_PAGE2, 2, 0x62, 3, 3, CHG_NZV, cpu9s12x, 0 },
+ { "incw", OP_IDX_1 | OP_PAGE2, 3, 0x62, 4, 4, CHG_NZV, cpu9s12x, 0 },
+ { "incw", OP_IDX_2 | OP_PAGE2, 4, 0x62, 5, 5, CHG_NZV, cpu9s12x, 0 },
+ { "incw", OP_D_IDX | OP_PAGE2, 2, 0x62, 6, 6, CHG_NZV, cpu9s12x, 0 },
+ { "incw", OP_D_IDX_2 | OP_PAGE2, 4, 0x62, 6, 6, CHG_NZV, cpu9s12x, 0 },
+
+ { "incx", OP_NONE | OP_PAGE2, 3, 0x42, 4, 4, CHG_NZV, cpu9s12x, 0 },
+
+ { "incy", OP_NONE | OP_PAGE2, 3, 0x52, 4, 4, CHG_NZV, cpu9s12x, 0 },
+
+ { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811, 0 },
+
+ { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811, 0 },
+ { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812|cpu9s12x, 0 },
+
+ { "jmp", OP_IND16 | OP_BRANCH, 3, 0x7e, 3, 3, CHG_NONE, cpu6811, 0 },
+ { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811, 0 },
+ { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811, 0 },
+ { "jmp", OP_IND16 | OP_BRANCH, 3, 0x06, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x9d, 5, 5, CHG_NONE, cpu6811, 0 },
+ { "jsr", OP_IND16 | OP_BRANCH, 3, 0xbd, 6, 6, CHG_NONE, cpu6811, 0 },
+ { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811, 0 },
+ { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811, 0 },
+ { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x17, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jsr", OP_IND16 | OP_BRANCH, 3, 0x16, 4, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811, 0 },
+ { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+/* lslw is the same as aslw. */
+ { "lslw", OP_IND16 | OP_PAGE2, 3, 0x78, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "lslw", OP_IDX | OP_PAGE2, 2, 0x68, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "lslw", OP_IDX_1 | OP_PAGE2, 3, 0x68, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "lslw", OP_IDX_2 | OP_PAGE2, 4, 0x68, 5, 5, CHG_NZVC, cpu9s12x, 0 },
+ { "lslw", OP_D_IDX | OP_PAGE2, 2, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "lslw", OP_D_IDX_2 | OP_PAGE2, 4, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+/* lslx is same as aslx. */
+ { "lslx", OP_NONE | OP_PAGE2, 1, 0x48, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+/* lsly is the same as asly. */
+ { "lsly", OP_NONE | OP_PAGE2, 1, 0x58, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811, 0 },
+ { "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811, 0 },
+ { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
+ { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
+ { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
+ { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
+ { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
+
+ { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811, 0 },
+ { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
+
+ { "lsrw", OP_IND16 | OP_PAGE2, 3, 0x74, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "lsrw", OP_IDX | OP_PAGE2, 2, 0x64, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "lsrw", OP_IDX_1 | OP_PAGE2, 3, 0x64, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "lsrw", OP_IDX_2 | OP_PAGE2, 4, 0x64, 5, 5, CHG_NZVC, cpu9s12x, 0 },
+ { "lsrw", OP_D_IDX | OP_PAGE2, 2, 0x64, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "lsrw", OP_D_IDX_2 | OP_PAGE2, 4, 0x64, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "lsrx", OP_NONE | OP_PAGE2, 1, 0x44, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "lsry", OP_NONE | OP_PAGE2, 1, 0x54, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+
+ { "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+/* The S12X additional modes are implemented, but uncommenting here causes a problem */
+ { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+/* { "movb", OP_IMM8|OP_IDX1_p2|OP_PAGE2, 5, 0x08, 4, 4, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IMM8|OP_IDX2_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IMM8|OP_D_IDX|OP_PAGE2, 5, 0x08, 4, 4, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IMM8|OP_D_IDX2_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu9s12x, 0 },*/
+
+ { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "movb", OP_IND16|OP_IDX_p2|OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
+/* { "movb", OP_IND16|OP_IDX1_p2|OP_PAGE2, 6, 0x09, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IND16|OP_IDX2_p2|OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IND16|OP_D_IDX_p2|OP_PAGE2, 6, 0x09, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IND16|OP_D_IDX2_p2|OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu9s12x, 0 }, */
+
+ { "movb", OP_IDX|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "movb", OP_IDX|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
+/* { "movb", OP_IDX|OP_IDX1_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX|OP_IDX2_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX|OP_D_IDX_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX|OP_D_IDX2_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+
+ { "movb", OP_IDX_1|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_1|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_1|OP_IDX1_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_1|OP_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_1|OP_D_IDX_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_1|OP_D_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+
+ { "movb", OP_IDX_2|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_2|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_2|OP_IDX1_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_2|OP_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_2|OP_D_IDX_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_IDX_2|OP_D_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+
+ { "movb", OP_D_IDX|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX|OP_IDX1_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX|OP_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX|OP_D_IDX_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX|OP_D_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+
+ { "movb", OP_D_IDX_2|OP_IND16_p2|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX_2|OP_IDX_p2|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX_2|OP_IDX1_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX_2|OP_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX_2|OP_D_IDX_p2|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movb", OP_D_IDX_2|OP_D_IDX2_p2|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu9s12x, 0 },*/
+
+ { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812|cpu9s12x, 0 },
+/* { "movw", OP_IMM16|OP_IDX1_p2|OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IMM16|OP_IDX2_p2|OP_PAGE2, 4, 0x00, 4, 4, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IMM16|OP_D_IDX_p2|OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IMM16|OP_D_IDX2_p2|OP_PAGE2, 4, 0x00, 4, 4, CHG_NONE, cpu9s12x, 0 },*/
+
+ { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
+/* { "movw", OP_IND16|OP_IDX1_p2|OP_PAGE2, 6, 0x01, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IND16|OP_IDX2_p2|OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IND16|OP_D_IDX_p2|OP_PAGE2, 6, 0x01, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IND16|OP_D_IDX2_p2|OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu9s12x, 0 },*/
+
+ { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
+/* { "movw", OP_IDX|OP_IDX1_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX|OP_IDX2_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX|OP_D_IDX_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX|OP_D_IDX2_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+
+ { "movw", OP_IDX_1|OP_IND16_p2|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_1|OP_IDX_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_1|OP_IDX1_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_1|OP_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_1|OP_D_IDX_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_1|OP_D_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+
+ { "movw", OP_IDX_2|OP_IND16_p2|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_2|OP_IDX_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_2|OP_IDX1_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_2|OP_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_2|OP_D_IDX_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_IDX_2|OP_D_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+
+ { "movw", OP_D_IDX|OP_IND16_p2|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX|OP_IDX_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX|OP_IDX1_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX|OP_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX|OP_D_IDX_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX|OP_D_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+
+ { "movw", OP_D_IDX_2|OP_IND16_p2|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX_2|OP_IDX_p2|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX_2|OP_IDX1_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX_2|OP_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX_2|OP_D_IDX_p2|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu9s12x, 0 },
+ { "movw", OP_D_IDX_2|OP_D_IDX2_p2|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9s12x, 0 },*/
+
+ { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811, 0 },
+ { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812|cpu9s12x, 0 },
+
+ { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+
+ { "negw", OP_IND16| OP_PAGE2, 3, 0x70, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "negw", OP_IDX| OP_PAGE2, 2, 0x60, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "negw", OP_IDX_1| OP_PAGE2, 3, 0x60, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "negw", OP_IDX_2| OP_PAGE2, 4, 0x60, 5, 5, CHG_NZVC, cpu9s12x, 0 },
+ { "negw", OP_D_IDX| OP_PAGE2, 2, 0x60, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "negw", OP_D_IDX_2| OP_PAGE2, 4, 0x60, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "negx", OP_NONE| OP_PAGE2, 1, 0x40, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "negy", OP_NONE| OP_PAGE2, 1, 0x50, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811, 0 },
+ { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812|cpu9s12x, 0 },
+
+ { "orx", OP_IMM16| OP_PAGE2, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "orx", OP_DIRECT| OP_PAGE2, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "orx", OP_IND16| OP_PAGE2, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "orx", OP_IDX| OP_PAGE2, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "orx", OP_IDX_1| OP_PAGE2, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "orx", OP_IDX_2| OP_PAGE2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "orx", OP_D_IDX| OP_PAGE2, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "orx", OP_D_IDX_2| OP_PAGE2,4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "ory", OP_IMM16| OP_PAGE2, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "ory", OP_DIRECT| OP_PAGE2, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "ory", OP_IND16| OP_PAGE2, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "ory", OP_IDX| OP_PAGE2, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "ory", OP_IDX_1| OP_PAGE2, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "ory", OP_IDX_2| OP_PAGE2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "ory", OP_D_IDX| OP_PAGE2, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+ { "ory", OP_D_IDX_2| OP_PAGE2,4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },
+
+ { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "pshcw", OP_NONE| OP_PAGE2,1, 0x39, 2, 2, CHG_NONE, cpu9s12x, 0 },
+ { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811, 0 },
+ { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811, 0 },
+ { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "pulcw", OP_NONE| OP_PAGE2,1, 0x38, 2, 2, CHG_NONE, cpu9s12x, 0 },
+ { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811, 0 },
+ { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811, 0 },
+ { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+ { "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812|cpu9s12x, 0 },
+
+ { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811, 0 },
+ { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811, 0 },
+ { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "rolw", OP_IND16 | OP_PAGE2, 3, 0x75, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "rolw", OP_IDX | OP_PAGE2, 2, 0x65, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "rolw", OP_IDX_1 | OP_PAGE2, 3, 0x65, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "rolw", OP_IDX_2 | OP_PAGE2, 4, 0x65, 5, 5, CHG_NZVC, cpu9s12x, 0 },
+ { "rolw", OP_D_IDX | OP_PAGE2, 2, 0x65, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "rolw", OP_D_IDX_2 | OP_PAGE2, 4, 0x65, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "rolx", OP_NONE | OP_PAGE2, 1, 0x45, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+ { "roly", OP_NONE | OP_PAGE2, 1, 0x55, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+
+ { "rorw", OP_IND16 | OP_PAGE2, 3, 0x76, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "rorw", OP_IDX | OP_PAGE2, 2, 0x66, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "rorw", OP_IDX_1 | OP_PAGE2, 3, 0x66, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "rorw", OP_IDX_2 | OP_PAGE2, 4, 0x66, 5, 5, CHG_NZVC, cpu9s12x, 0 },
+ { "rorw", OP_D_IDX | OP_PAGE2, 2, 0x66, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "rorw", OP_D_IDX_2 | OP_PAGE2, 4, 0x66, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "rorx", OP_NONE | OP_PAGE2, 1, 0x46, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+ { "rory", OP_NONE | OP_PAGE2, 1, 0x56, 1, 1, CHG_NZVC, cpu9s12x, 0 },
+
+ { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812|cpu9s12x, 0 },
+ { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811, 0 },
+ { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812|cpu9s12x, 0 },
+ { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811, 0 },
+ { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811, 0 },
+ { "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811, 0 },
+ { "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811, 0 },
+ { "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "sbed", OP_IMM16 | OP_PAGE2, 3, 0x83, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "sbed", OP_DIRECT | OP_PAGE2, 2, 0x93, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbed", OP_IND16 | OP_PAGE2, 3, 0xb3, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbed", OP_IDX | OP_PAGE2, 2, 0xa3, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbed", OP_IDX_1 | OP_PAGE2, 3, 0xa3, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbed", OP_IDX_2 | OP_PAGE2, 4, 0xa3, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "sbed", OP_D_IDX | OP_PAGE2, 2, 0xa3, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "sbed", OP_D_IDX_2 | OP_PAGE2, 4, 0xa3, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "sbex", OP_IMM16 | OP_PAGE2, 3, 0x82, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "sbex", OP_DIRECT | OP_PAGE2, 2, 0x92, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbex", OP_IND16 | OP_PAGE2, 3, 0xb2, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbex", OP_IDX | OP_PAGE2, 2, 0xa2, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbex", OP_IDX_1 | OP_PAGE2, 3, 0xa2, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbex", OP_IDX_2 | OP_PAGE2, 4, 0xa2, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "sbex", OP_D_IDX | OP_PAGE2, 2, 0xa2, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "sbex", OP_D_IDX_2 | OP_PAGE2, 4, 0xa2, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "sbey", OP_IMM16 | OP_PAGE2, 3, 0xc2, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "sbey", OP_DIRECT | OP_PAGE2, 2, 0xd2, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbey", OP_IND16 | OP_PAGE2, 3, 0xf2, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbey", OP_IDX | OP_PAGE2, 2, 0xe2, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbey", OP_IDX_1 | OP_PAGE2, 3, 0xe2, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "sbey", OP_IDX_2 | OP_PAGE2, 4, 0xe2, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "sbey", OP_D_IDX | OP_PAGE2, 2, 0xe2, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "sbey", OP_D_IDX_2 | OP_PAGE2, 4, 0xe2, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811, 0 },
+ { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811, 0 },
+ { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811, 0 },
+
+/* Some sex opcodes are synonyms for tfr. */
{ "sex", M6812_OP_SEX_MARKER
- | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },
-
- { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811 },
- { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 },
- { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 },
-
- { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811 },
- { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 },
- { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 },
-
- { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 },
- { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 },
-
- { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811 },
- { "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812 },
-
- { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 },
- { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 },
-
- { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811 },
- { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 },
- { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 },
-
- { "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811 },
- { "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },
- { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812 },
- { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 },
- { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 },
- { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 },
-
- { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811 },
- { "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811 },
- { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812 },
- { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812 },
- { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812 },
- { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812 },
- { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812 },
-
- { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812 },
- { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811 },
- { "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811 },
- { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812 },
- { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812 },
- { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812 },
- { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812 },
- { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812 },
-
- { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812 },
- { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812 },
- { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811 },
- { "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },
- { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812 },
- { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812 },
- { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812 },
- { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812 },
- { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812 },
-
- { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812 },
-
- { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811 },
- { "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812 },
-
- { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811 },
-
- { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811 },
- { "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812 },
-
- { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 },
-
- { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811 },
+ | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811, 0 },
+ { "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811, 0 },
+ { "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811, 0 },
+ { "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811, 0 },
+ { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811, 0 },
+ { "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811, 0 },
+ { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+ { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812|cpu9s12x, 0 },
+
+ { "subx", OP_IMM16 | OP_PAGE2, 3, 0x80, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "subx", OP_DIRECT | OP_PAGE2, 2, 0x90, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "subx", OP_IND16 | OP_PAGE2, 3, 0xb0, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "subx", OP_IDX | OP_PAGE2, 2, 0xa0, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "subx", OP_IDX_1 | OP_PAGE2, 3, 0xa0, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "subx", OP_IDX_2 | OP_PAGE2, 4, 0xa0, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "subx", OP_D_IDX | OP_PAGE2, 2, 0xa0, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "subx", OP_D_IDX_2 | OP_PAGE2, 4, 0xa0, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "suby", OP_IMM16 | OP_PAGE2, 3, 0xc0, 2, 2, CHG_NZVC, cpu9s12x, 0 },
+ { "suby", OP_DIRECT | OP_PAGE2, 2, 0xd0, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "suby", OP_IND16 | OP_PAGE2, 3, 0xf0, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "suby", OP_IDX | OP_PAGE2, 2, 0xe0, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "suby", OP_IDX_1 | OP_PAGE2, 3, 0xe0, 3, 3, CHG_NZVC, cpu9s12x, 0 },
+ { "suby", OP_IDX_2 | OP_PAGE2, 4, 0xe0, 4, 4, CHG_NZVC, cpu9s12x, 0 },
+ { "suby", OP_D_IDX | OP_PAGE2, 2, 0xe0, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+ { "suby", OP_D_IDX_2 | OP_PAGE2, 4, 0xe0, 6, 6, CHG_NZVC, cpu9s12x, 0 },
+
+ { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
+ { "sys", OP_NONE | OP_PAGE2,2, 0xa7, 9, 9, SET_I, cpu9s12x, 0 },
+
+ { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811, 0 },
+
+ { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811, 0 },
+ { "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811, 0 },
+
+ { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811, 0 },
{ "tbeq", OP_TBEQ_MARKER
- | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
+ | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
- { "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812 },
+ { "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812|cpu9s12x, 0 },
{ "tbne", OP_TBNE_MARKER
- | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },
+ | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812|cpu9s12x, 0 },
+/* The S12X has more tfr variants, but most are pointless so not supported. */
{ "tfr", OP_TFR_MARKER
- | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },
-
- { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812 },
-
- { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811 },
- { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811 },
- { "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811 },
- { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },
- { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },
- { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },
- { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812 },
- { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 },
- { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 },
-
- { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811 },
- { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812 },
- { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811 },
- { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812 },
-
- { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811 },
- { "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811 },
- { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811 },
- { "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811 },
-
- { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812 },
-
- { "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812 },
-
- { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811 },
- { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811 }
+ | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812|cpu9s12x, 0 },
+
+ { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812|cpu9s12x, 0 },
+
+ { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811, 0 },
+ { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811, 0 },
+ { "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811, 0 },
+ { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811, 0 },
+ { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
+ { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811, 0 },
+ { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
+
+ { "tstw", OP_IND16| OP_PAGE2, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu9s12x, 0 },
+ { "tstw", OP_IDX| OP_PAGE2, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu9s12x, 0 },
+ { "tstw", OP_IDX_1| OP_PAGE2, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu9s12x, 0 },
+ { "tstw", OP_IDX_2| OP_PAGE2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu9s12x, 0 },
+ { "tstw", OP_D_IDX| OP_PAGE2, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu9s12x, 0 },
+ { "tstw", OP_D_IDX_2| OP_PAGE2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu9s12x, 0 },
+
+ { "tstx", OP_NONE| OP_PAGE2, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu9s12x, 0 },
+ { "tsty", OP_NONE| OP_PAGE2, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu9s12x, 0 },
+
+ { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811, 0 },
+ { "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811, 0 },
+ { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811, 0 },
+ { "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811, 0 },
+
+ { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
+
+ { "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812|cpu9s12x, 0 },
+
+ { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811, 0 },
+ { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811, 0 },
+
+/* XGATE opcodes */
+/* Return to Scheduler and Others*/
+ { "brk", M68XG_OP_NONE, 2, 0x0000, 0, 0, 0, 0, 0, cpuxgate, 0xffff },
+ { "nop", M68XG_OP_NONE, 2, 0x0100, 0, 0, 0, 0, 0, cpuxgate, 0xffff },
+ { "rts", M68XG_OP_NONE, 2, 0x0200, 0, 0, 0, 0, 0, cpuxgate, 0xffff },
+ { "sif", M68XG_OP_NONE, 2, 0x0300, 0, 0, 0, 0, 0, cpuxgate, 0xffff },
+/* Semaphore Instructions */
+ { "csem", M68XG_OP_IMM3, 2, 0x00f0, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
+ { "csem", M68XG_OP_R, 2, 0x00f1, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
+ { "ssem", M68XG_OP_IMM3, 2, 0x00f2, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
+ { "ssem", M68XG_OP_R, 2, 0x00f3, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
+/* Single Register Instructions */
+ { "sex", M68XG_OP_R, 2, 0x00f4, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
+ { "par", M68XG_OP_R, 2, 0x00f5, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
+ { "jal", M68XG_OP_R, 2, 0x00f6, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
+ { "sif", M68XG_OP_R, 2, 0x00f7, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
+/* Special Move instructions */
+ { "tfr", M68XG_OP_R, 2, 0x00f8, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* RD,CCR */
+ { "tfr", M68XG_OP_R, 2, 0x00f9, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* CCR,RS */
+ { "tfr", M68XG_OP_R, 2, 0x00fa, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* RD,PC */
+/* Shift instructions Dyadic */
+ { "bffo", M68XG_OP_R_R, 2, 0x0810, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
+ { "asr", M68XG_OP_R_R, 2, 0x0811, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
+ { "csl", M68XG_OP_R_R, 2, 0x0812, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
+ { "csr", M68XG_OP_R_R, 2, 0x0813, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
+ { "lsl", M68XG_OP_R_R, 2, 0x0814, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
+ { "lsr", M68XG_OP_R_R, 2, 0x0815, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
+ { "rol", M68XG_OP_R_R, 2, 0x0816, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
+ { "ror", M68XG_OP_R_R, 2, 0x0817, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
+/* Dyadic aliases */
+ { "cmp", M68XG_OP_R_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "com", M68XG_OP_R_R, 2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "cpc", M68XG_OP_R_R, 2, 0x1801, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "mov", M68XG_OP_R_R, 2, 0x1002, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "neg", M68XG_OP_R_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+/* Monadic aliases */
+ { "com", M68XG_OP_R, 2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "neg", M68XG_OP_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "tst", M68XG_OP_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+/* Shift instructions immediate */
+ { "asr", M68XG_OP_R_IMM4, 2, 0x0809, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
+ { "csl", M68XG_OP_R_IMM4, 2, 0x080a, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
+ { "csr", M68XG_OP_R_IMM4, 2, 0x080b, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
+ { "lsl", M68XG_OP_R_IMM4, 2, 0x080c, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
+ { "lsr", M68XG_OP_R_IMM4, 2, 0x080d, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
+ { "rol", M68XG_OP_R_IMM4, 2, 0x080e, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
+ { "ror", M68XG_OP_R_IMM4, 2, 0x080f, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
+/* Logical Triadic */
+ { "and", M68XG_OP_R_R_R, 2, 0x1000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "or", M68XG_OP_R_R_R, 2, 0x1002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "xnor", M68XG_OP_R_R_R, 2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+/* Arithmetic Triadic */
+ { "sub", M68XG_OP_R_R_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "sbc", M68XG_OP_R_R_R, 2, 0x1801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "add", M68XG_OP_R_R_R, 2, 0x1802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "adc", M68XG_OP_R_R_R, 2, 0x1803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+/* Branches */
+ { "bcc", M68XG_OP_REL9, 2, 0x2000, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bhs", M68XG_OP_REL9, 2, 0x2000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, /* Synonym. */
+ { "bcs", M68XG_OP_REL9, 2, 0x2200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "blo", M68XG_OP_REL9, 2, 0x2200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, /* Synonym. */
+ { "bne", M68XG_OP_REL9, 2, 0x2400, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "beq", M68XG_OP_REL9, 2, 0x2600, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bpl", M68XG_OP_REL9, 2, 0x2800, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bmi", M68XG_OP_REL9, 2, 0x2a00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bvc", M68XG_OP_REL9, 2, 0x2c00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bvs", M68XG_OP_REL9, 2, 0x2e00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bhi", M68XG_OP_REL9, 2, 0x3000, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bls", M68XG_OP_REL9, 2, 0x3200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bge", M68XG_OP_REL9, 2, 0x3400, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "blt", M68XG_OP_REL9, 2, 0x3600, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bgt", M68XG_OP_REL9, 2, 0x3800, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "ble", M68XG_OP_REL9, 2, 0x3a00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
+ { "bra", M68XG_OP_REL10, 2, 0x3c00, 0, 0, 0, 0, 0, cpuxgate, 0xfc00 },
+/* Load and Store Instructions */
+ { "ldb", M68XG_OP_R_R_OFFS5, 2, 0x4000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "ldw", M68XG_OP_R_R_OFFS5, 2, 0x4800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "stb", M68XG_OP_R_R_OFFS5, 2, 0x5000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "stw", M68XG_OP_R_R_OFFS5, 2, 0x5800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+
+ { "ldb", M68XG_OP_RD_RB_RI, 2, 0x6000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "ldw", M68XG_OP_RD_RB_RI, 2, 0x6800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "stb", M68XG_OP_RD_RB_RI, 2, 0x7000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "stw", M68XG_OP_RD_RB_RI, 2, 0x7800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+
+ { "ldb", M68XG_OP_RD_RB_RIp, 2, 0x6001, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "ldw", M68XG_OP_RD_RB_RIp, 2, 0x6801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "stb", M68XG_OP_RD_RB_RIp, 2, 0x7001, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "stw", M68XG_OP_RD_RB_RIp, 2, 0x7801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+
+ { "ldb", M68XG_OP_RD_RB_mRI, 2, 0x6002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "ldw", M68XG_OP_RD_RB_mRI, 2, 0x6802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "stb", M68XG_OP_RD_RB_mRI, 2, 0x7002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "stw", M68XG_OP_RD_RB_mRI, 2, 0x7802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+/* Bit Field Instructions */
+ { "bfext", M68XG_OP_R_R_R, 2, 0x6003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "bfins", M68XG_OP_R_R_R, 2, 0x6803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "bfinsi",M68XG_OP_R_R_R, 2, 0x7003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+ { "bfinsx",M68XG_OP_R_R_R, 2, 0x7803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
+/* Logic Immediate Instructions */
+ { "andl", M68XG_OP_R_IMM8, 2, 0x8000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "andh", M68XG_OP_R_IMM8, 2, 0x8800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "bitl", M68XG_OP_R_IMM8, 2, 0x9000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "bith", M68XG_OP_R_IMM8, 2, 0x9800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "orl", M68XG_OP_R_IMM8, 2, 0xa000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "orh", M68XG_OP_R_IMM8, 2, 0xa800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "xnorl", M68XG_OP_R_IMM8, 2, 0xb000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "xnorh", M68XG_OP_R_IMM8, 2, 0xb800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+/* Arithmetic Immediate Instructions */
+ { "subl", M68XG_OP_R_IMM8, 2, 0xc000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "subh", M68XG_OP_R_IMM8, 2, 0xc800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "cmpl", M68XG_OP_R_IMM8, 2, 0xd000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "cpch", M68XG_OP_R_IMM8, 2, 0xd800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "addl", M68XG_OP_R_IMM8, 2, 0xe000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "addh", M68XG_OP_R_IMM8, 2, 0xe800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "ldl", M68XG_OP_R_IMM8, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+ { "ldh", M68XG_OP_R_IMM8, 2, 0xf800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
+/* 16 bit versions.
+ * These are pseudo opcodes to allow 16 bit addresses to be passed.
+ * The mask ensures that we will never disassemble to these instructions.
+ */
+/* Logic Immediate Instructions */
+ { "and", M68XG_OP_R_IMM16, 2, 0x8000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "bit", M68XG_OP_R_IMM16, 2, 0x9000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "or", M68XG_OP_R_IMM16, 2, 0xa000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "xnor", M68XG_OP_R_IMM16, 2, 0xb000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+/* Arithmetic Immediate Instructions */
+ { "sub", M68XG_OP_R_IMM16, 2, 0xc000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "cmp", M68XG_OP_R_IMM16, 2, 0xd000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "add", M68XG_OP_R_IMM16, 2, 0xe000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ /* ld is for backwards compatability only, the correct opcode is ldw */
+ { "ld", M68XG_OP_R_IMM16, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
+ { "ldw", M68XG_OP_R_IMM16, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }
};
const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes);