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authorPalmer Dabbelt <palmer@sifive.com>2018-10-02 08:26:32 -0700
committerPalmer Dabbelt <palmer@sifive.com>2018-10-02 08:26:32 -0700
commit64a336ac134ebd7f9452a7088e90e29551465251 (patch)
tree43af5101dd733eaef5710e6ead74105397cc20ee /opcodes
parentc1168a2f66553cd4730931cf59e3be8378a1a03f (diff)
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RISC-V: Add fence.tso instruction
The RISC-V memory model has been ratified, and it includes an additional fence: "fence.tso". This pseudo instruction extends one of the previously reserved full fence patterns to be less restrictive, and therefor will execute correctly on all existing microarchitectures. Thus there is no reason to allow this instruction to be disabled (or unconverted to a full fence), so it's just unconditionally allowed. I've added a test case for GAS to check that "fence.tso" correctly assembles on rv32i-based targets. I checked to see that "fence.tso" appears in "gas.log", but that's the only testing I've done. gas/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * testsuite/gas/riscv/fence-tso.d: New file. * testsuite/gas/riscv/fence-tso.s: Likewise. include/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define. (MASK_FENCE_TSO): Likewise. opcodes/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/riscv-opc.c1
2 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9b68285..54baef0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2018-10-02 Palmer Dabbelt <palmer@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
+
2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
* nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e0f7118..b6843f2 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -342,6 +342,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"fence", 0, {"I", 0}, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, {"I", 0}, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
{"fence.i", 0, {"I", 0}, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
+{"fence.tso", 0, {"I", 0}, "", MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS },
{"rdcycle", 0, {"I", 0}, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
{"rdinstret", 0, {"I", 0}, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
{"rdtime", 0, {"I", 0}, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },