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authorJulian Brown <julian@codesourcery.com>2007-01-04 15:33:12 +0000
committerJulian Brown <julian@codesourcery.com>2007-01-04 15:33:12 +0000
commit62ac925e42ad66c2faf59bd78e182f822760bb56 (patch)
tree99a56a2466660cce6cd0a4303f195beb67996de2 /opcodes
parent627907b7d8b96d26997dc649bebaab6df7071ea3 (diff)
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* arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl,
vqrshl instructions.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/arm-dis.c8
2 files changed, 9 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index cc5ec75..f5cb698 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2007-01-04 Julian Brown <julian@codesourcery.com>
+
+ * arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl,
+ vqrshl instructions.
+
2006-12-27 Kazu Hirata <kazu@codesourcery.com>
* m68k-dis.c (print_insn_arg): Add support for cac and mbb.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 49765d8..a1f250c 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -576,10 +576,10 @@ static const struct opcode32 neon_opcodes[] =
{FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
+ {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
+ {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
+ {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
{FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},