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authorDavid Guillen Fandos <david@davidgf.net>2024-06-11 09:36:11 +0100
committerMaciej W. Rozycki <macro@redhat.com>2024-06-11 09:36:11 +0100
commit60e221e9b7fae5ff40b79b93bdbff909989c2bae (patch)
tree7182cd55c7d812f09e07bc35f73eb4d94e09bf3e /opcodes
parent1ded0d12e0ee5399a3c1d8606fd23491e00fc60f (diff)
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MIPS/opcodes: Add MIPS Allegrex DBREAK instruction
This complements the debug instruction set and uses the same encoding as the VR5400/VR5500 devices.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/mips-opc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index a31a17d..c6cbb66 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1030,7 +1030,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
-{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
+{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL, 0, 0 },
{"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
{"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
{"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },