aarch64: Rename za_tile_vector to za_index

za_tile_vector is also used for indexing ZA as a whole, rather than
just for indexing tiles.  The former is more common than the latter
in SME2, so this patch generalises the name to "indexed_za".

The patch also names the associated structure, so that later patches
can reuse it during parsing.

3 files changed, 36 insertions, 36 deletions

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index bfabcb9..73ee15a 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1340,10 +1340,10 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self,
 {
   int fld_size;
   int fld_q;
-  int fld_v = info->za_tile_vector.v;
-  int fld_rv = info->za_tile_vector.index.regno - 12;
-  int fld_zan_imm = info->za_tile_vector.index.imm;
-  int regno = info->za_tile_vector.regno;
+  int fld_v = info->indexed_za.v;
+  int fld_rv = info->indexed_za.index.regno - 12;
+  int fld_zan_imm = info->indexed_za.index.imm;
+  int regno = info->indexed_za.regno;
 
   switch (info->qualifier)
     {
@@ -1410,8 +1410,8 @@ aarch64_ins_sme_za_array (const aarch64_operand *self,
                           const aarch64_inst *inst ATTRIBUTE_UNUSED,
                           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
-  int regno = info->za_tile_vector.index.regno - 12;
-  int imm = info->za_tile_vector.index.imm;
+  int regno = info->indexed_za.index.regno - 12;
+  int imm = info->indexed_za.index.imm;
   insert_field (self->fields[0], code, regno, 0);
   insert_field (self->fields[1], code, imm, 0);
   return true;
@@ -1464,9 +1464,9 @@ aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self,
                                      const aarch64_inst *inst ATTRIBUTE_UNUSED,
                                      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
-  int fld_pn = info->za_tile_vector.regno;
-  int fld_rm = info->za_tile_vector.index.regno - 12;
-  int imm = info->za_tile_vector.index.imm;
+  int fld_pn = info->indexed_za.regno;
+  int fld_rm = info->indexed_za.index.regno - 12;
+  int imm = info->indexed_za.index.imm;
   int fld_i1, fld_tszh, fld_tshl;
 
   insert_field (self->fields[0], code, fld_rm, 0);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 01881ea..eabcc9e 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1786,34 +1786,34 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
   /* Deduce qualifier encoded in size and Q fields.  */
   if (fld_size == 0)
     {
-      info->za_tile_vector.regno = 0;
-      info->za_tile_vector.index.imm = fld_zan_imm;
+      info->indexed_za.regno = 0;
+      info->indexed_za.index.imm = fld_zan_imm;
     }
   else if (fld_size == 1)
     {
-      info->za_tile_vector.regno = fld_zan_imm >> 3;
-      info->za_tile_vector.index.imm = fld_zan_imm & 0x07;
+      info->indexed_za.regno = fld_zan_imm >> 3;
+      info->indexed_za.index.imm = fld_zan_imm & 0x07;
     }
   else if (fld_size == 2)
     {
-      info->za_tile_vector.regno = fld_zan_imm >> 2;
-      info->za_tile_vector.index.imm = fld_zan_imm & 0x03;
+      info->indexed_za.regno = fld_zan_imm >> 2;
+      info->indexed_za.index.imm = fld_zan_imm & 0x03;
     }
   else if (fld_size == 3 && fld_q == 0)
     {
-      info->za_tile_vector.regno = fld_zan_imm >> 1;
-      info->za_tile_vector.index.imm = fld_zan_imm & 0x01;
+      info->indexed_za.regno = fld_zan_imm >> 1;
+      info->indexed_za.index.imm = fld_zan_imm & 0x01;
     }
   else if (fld_size == 3 && fld_q == 1)
     {
-      info->za_tile_vector.regno = fld_zan_imm;
-      info->za_tile_vector.index.imm = 0;
+      info->indexed_za.regno = fld_zan_imm;
+      info->indexed_za.index.imm = 0;
     }
   else
     return false;
 
-  info->za_tile_vector.index.regno = fld_rv + 12;
-  info->za_tile_vector.v = fld_v;
+  info->indexed_za.index.regno = fld_rv + 12;
+  info->indexed_za.v = fld_v;
 
   return true;
 }
@@ -1847,8 +1847,8 @@ aarch64_ext_sme_za_array (const aarch64_operand *self,
 {
   int regno = extract_field (self->fields[0], code, 0) + 12;
   int imm = extract_field (self->fields[1], code, 0);
-  info->za_tile_vector.index.regno = regno;
-  info->za_tile_vector.index.imm = imm;
+  info->indexed_za.index.regno = regno;
+  info->indexed_za.index.imm = imm;
   return true;
 }
 
@@ -1902,8 +1902,8 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
   aarch64_insn fld_tszl = extract_field (self->fields[4], code, 0);
   int imm;
 
-  info->za_tile_vector.regno = fld_pn;
-  info->za_tile_vector.index.regno = fld_rm + 12;
+  info->indexed_za.regno = fld_pn;
+  info->indexed_za.index.regno = fld_rm + 12;
 
   if (fld_tszl & 0x1)
     imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
@@ -1916,7 +1916,7 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
   else
     return false;
 
-  info->za_tile_vector.index.imm = imm;
+  info->indexed_za.index.imm = imm;
   return true;
 }
 
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a0e6240..bbbac41 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2770,7 +2770,7 @@ aarch64_match_operands_constraint (aarch64_inst *inst,
         case sme_str:
           assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array);
           assert (inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVL);
-          if (inst->operands[0].za_tile_vector.index.imm
+          if (inst->operands[0].indexed_za.index.imm
               != inst->operands[1].addr.offset.imm)
             {
               if (mismatch_detail)
@@ -3556,11 +3556,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
       snprintf (buf, size, "%s%s[%s, %s]%s",
 		opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
 		style_reg (styler, "za%d%c.%s",
-			   opnd->za_tile_vector.regno,
-			   opnd->za_tile_vector.v == 1 ? 'v' : 'h',
+			   opnd->indexed_za.regno,
+			   opnd->indexed_za.v == 1 ? 'v' : 'h',
 			   aarch64_get_qualifier_name (opnd->qualifier)),
-		style_reg (styler, "w%d", opnd->za_tile_vector.index.regno),
-		style_imm (styler, "%d", opnd->za_tile_vector.index.imm),
+		style_reg (styler, "w%d", opnd->indexed_za.index.regno),
+		style_imm (styler, "%d", opnd->indexed_za.index.imm),
 		opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : "");
       break;
 
@@ -3571,8 +3571,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SME_ZA_array:
       snprintf (buf, size, "%s[%s, %s]",
 		style_reg (styler, "za"),
-		style_reg (styler, "w%d", opnd->za_tile_vector.index.regno),
-		style_imm (styler, "%d", opnd->za_tile_vector.index.imm));
+		style_reg (styler, "w%d", opnd->indexed_za.index.regno),
+		style_imm (styler, "%d", opnd->indexed_za.index.imm));
       break;
 
     case AARCH64_OPND_SME_SM_ZA:
@@ -3582,10 +3582,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 
     case AARCH64_OPND_SME_PnT_Wm_imm:
       snprintf (buf, size, "%s[%s, %s]",
-		style_reg (styler, "p%d.%s", opnd->za_tile_vector.regno,
+		style_reg (styler, "p%d.%s", opnd->indexed_za.regno,
 			   aarch64_get_qualifier_name (opnd->qualifier)),
-                style_reg (styler, "w%d", opnd->za_tile_vector.index.regno),
-                style_imm (styler, "%d", opnd->za_tile_vector.index.imm));
+		style_reg (styler, "w%d", opnd->indexed_za.index.regno),
+		style_imm (styler, "%d", opnd->indexed_za.index.imm));
       break;
 
     case AARCH64_OPND_CRn: