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authorMaciej W. Rozycki <macro@codesourcery.com>2014-08-26 13:44:34 +0100
committerMaciej W. Rozycki <macro@codesourcery.com>2014-08-26 13:44:34 +0100
commit5575639b8dbb2a04087c3bef0b10f182da48ad35 (patch)
tree78b3908ad5220a6b8cb90396ab42ca8e6412c1d6 /opcodes
parent0db377d09c19fc0f9267ead1f75998b9f1eb38d1 (diff)
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MIPS: Make the CODE10 operand code consistent between ISAs
This change moves the microMIPS 10-bit uninterpreted immediate code embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL instructions from `B' over to `+J' which is the operand code used in the standard MIPS instruction set for a similar code embedded at bits 20..11, currently used by HYPCALL only in that set. opcodes/ * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'. (micromips_opcodes): Use "+J" in place of "B" for "hypcall", "sdbbp", "syscall" and "wait". include/opcode/ * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' over to `+J'.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/micromips-opc.c10
2 files changed, 11 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a9581ae..ca42dc9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
+ (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
+ "sdbbp", "syscall" and "wait".
+
2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 4bf8241..71b2dfe 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -107,6 +107,7 @@ decode_micromips_operand (const char *p)
case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */
case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */
case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */
+ case 'J': HINT (10, 16);
case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */
case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */
case 'V': INT_ADJ (10, 16, 511, 2, FALSE); /* (-512 .. 511) << 2 */
@@ -158,7 +159,6 @@ decode_micromips_operand (const char *p)
case '7': REG (2, 14, ACC);
case '8': HINT (6, 14);
- case 'B': HINT (10, 16);
case 'C': HINT (23, 3);
case 'D': REG (5, 11, FP);
case 'E': REG (5, 21, COPRO);
@@ -688,7 +688,7 @@ const struct mips_opcode micromips_opcodes[] =
{"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
{"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 },
-{"hypcall", "B", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 },
+{"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 },
{"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 },
{"iret", "", 0x0000d37c, 0xffffffff, NODS, 0, 0, MC, 0 },
{"jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 },
@@ -963,7 +963,7 @@ const struct mips_opcode micromips_opcodes[] =
{"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1, 0, 0 },
{"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1, 0, 0 },
{"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1, 0, 0 },
-{"sdbbp", "B", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
+{"sdbbp", "+J", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
{"sdc1", "T,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 },
{"sdc1", "E,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
@@ -1066,7 +1066,7 @@ const struct mips_opcode micromips_opcodes[] =
{"sync", "1", 0x00006b7c, 0xffe0ffff, NODS, 0, I1, 0, 0 },
{"synci", "o(b)", 0x42000000, 0xffe00000, RD_2|SM, 0, I1, 0, 0 },
{"syscall", "", 0x00008b7c, 0xffffffff, TRAP, 0, I1, 0, 0 },
-{"syscall", "B", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
+{"syscall", "+J", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
{"teqi", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 },
{"teq", "s,t", 0x0000003c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
{"teq", "s,t,|", 0x0000003c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
@@ -1121,7 +1121,7 @@ const struct mips_opcode micromips_opcodes[] =
{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, 0 },
{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, 0 },
{"wait", "", 0x0000937c, 0xffffffff, NODS, 0, I1, 0, 0 },
-{"wait", "B", 0x0000937c, 0xfc00ffff, NODS, 0, I1, 0, 0 },
+{"wait", "+J", 0x0000937c, 0xfc00ffff, NODS, 0, I1, 0, 0 },
{"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_2, 0, I1, 0, 0 },
{"wsbh", "t,r", 0x00007b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 },
{"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 },