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| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:01:18 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:01:18 +0000 |
| commit | 53c4b28b4f873fd41d158eb9f23b2d07e2780b98 (patch) | |
| tree | ee108b7763d5cb1be914bf911564fc8416b4ab34 /opcodes | |
| parent | e797f7e0b2bedc9328d4a9a0ebc63ca7a2dbbebc (diff) | |
| download | gdb-53c4b28b4f873fd41d158eb9f23b2d07e2780b98.zip gdb-53c4b28b4f873fd41d158eb9f23b2d07e2780b98.tar.gz gdb-53c4b28b4f873fd41d158eb9f23b2d07e2780b98.tar.bz2 | |
* gas/config/tc-arm.c (T16_32_TAB): Add _sevl.
(insns): Add SEVL.
* gas/testsuite/gas/arm/armv8-a.s: New testcase.
* gas/testsuite/gas/arm/armv8-a.d: Likewise.
* opcodes/arm-dis.c (arm_opcodes): Add SEVL.
(thumb_opcodes): Likewise.
(thumb32_opcodes): Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 9 |
2 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2b60eb5..b60b6af 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + * arm-dis.c (arm_opcodes): Add SEVL. + (thumb_opcodes): Likewise. + (thumb32_opcodes): Likewise. + +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + * arm-dis.c (data_barrier_option): New function. (print_insn_arm): Use data_barrier_option. (print_insn_thumb32): Use data_barrier_option. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index ccbb6b3..5a450d7 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -849,6 +849,9 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + /* V8 instructions. */ + {ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"}, + /* Virtualization Extension instructions. */ {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"}, {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, @@ -1244,6 +1247,9 @@ static const struct opcode16 thumb_opcodes[] = { /* Thumb instructions. */ + /* ARM V8 instructions. */ + {ARM_EXT_V8, 0xbf50, 0xffff, "sevl%c"}, + /* ARM V6K no-argument instructions. */ {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, @@ -1413,6 +1419,9 @@ static const struct opcode16 thumb_opcodes[] = makes heavy use of special-case bit patterns. */ static const struct opcode32 thumb32_opcodes[] = { + /* V8 instructions. */ + {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"}, + /* V7 instructions. */ {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, |