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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-06-27 11:03:44 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-07-07 12:06:02 +0800 |
| commit | 3d5d6bd55433735c4fc620a47b543065582d06ae (patch) | |
| tree | 7de69e8d4565d68c1eda18aaae0ac7185abf36d3 /opcodes | |
| parent | 37cf60c6a6d36bbf5cf1523697906c4bdb4eb468 (diff) | |
| download | gdb-3d5d6bd55433735c4fc620a47b543065582d06ae.zip gdb-3d5d6bd55433735c4fc620a47b543065582d06ae.tar.gz gdb-3d5d6bd55433735c4fc620a47b543065582d06ae.tar.bz2 | |
RISC-V: Fix disassembling Zfinx with -M numeric
This commit fixes floating point operand register names from ABI ones
to dynamically set ones.
gas/ChangeLog:
* testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of
Zfinx extension and -M numeric disassembler option.
* testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR
names to disassemble Zfinx instructions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-dis.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 9ff3116..164fd20 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -639,7 +639,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) /* If arch has ZFINX flags, use gpr for disassemble. */ if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) - riscv_fpr_names = riscv_gpr_names_abi; + riscv_fpr_names = riscv_gpr_names; for (; op->name; op++) { |