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| author | Thiemo Seufer <ths@networkno.de> | 2008-11-28 18:02:17 +0000 |
|---|---|---|
| committer | Thiemo Seufer <ths@networkno.de> | 2008-11-28 18:02:17 +0000 |
| commit | 3aa3176b2dea5796ab968b289804eced655f07ee (patch) | |
| tree | ad2039e6910f4951a98b3def13d245d7197b2638 /opcodes | |
| parent | 6fce36a432ae0879f863bd5d942ae17a5e36d297 (diff) | |
| download | gdb-3aa3176b2dea5796ab968b289804eced655f07ee.zip gdb-3aa3176b2dea5796ab968b289804eced655f07ee.tar.gz gdb-3aa3176b2dea5796ab968b289804eced655f07ee.tar.bz2 | |
* aoutx.h (NAME): Add case statements for bfd_mach_mips14000,
bfd_mach_mips16000.
* archures.c (bfd_architecture): Add .#defines for bfd_mach_mips14000,
bfd_mach_mips16000.
* bfd-in2.h: Regenerate.
* cpu-mips.c: Add enums I_mips14000, I_mips16000.
(arch_info_struct): Add refs to R14000, R16000.
* elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips14000,
bfd_mach_mips16000.
(mips_mach_extensions): Map R14000, R16000 to R10000.
* config/tc-mips.c (hilo_interlocks): Handle CPU_R14000, CPU_R16000.
(mips_cpu_info_table): Add r14000, r16000.
* doc/c-mips.texi: Add entries for 14000, 16000.
* mips-dis.c (mips_arch_choices): Add r14000, r16000.
* mips.h: Define CPU_R14000, CPU_R16000.
(OPCODE_IS_MEMBER): Include R14000, R16000 in test.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index cb072c7..dc62aa2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2008-11-28 Joshua Kinard <kumba@gentoo.org> + + * mips-dis.c (mips_arch_choices): Add r14000, r16000. + 2008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com> * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 7c38589..759e2aa 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -409,6 +409,10 @@ const struct mips_arch_choice mips_arch_choices[] = mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, |