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authorNick Clifton <nickc@redhat.com>2000-05-15 19:25:22 +0000
committerNick Clifton <nickc@redhat.com>2000-05-15 19:25:22 +0000
commit322f2c4579460de0fe10c89e9cd45588ae57b730 (patch)
treeebbb4a70bee123cdda0196ba5f6b838e1a4c60ba /opcodes
parent47cf603ed45d09dceda47b6da42a1d88a141ad82 (diff)
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Add support for _x and _s flags to MSR instruction
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog9
-rw-r--r--opcodes/arm-dis.c12
-rw-r--r--opcodes/arm-opc.h8
3 files changed, 22 insertions, 7 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c183c60..199e30f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2000-05-15 Nick Clifton <nickc@cygnus.com>
+
+ * arm-opc.h: Use upper case for flasg in MSR and MRS
+ instructions. Allow any bit to be set in the field_mask of
+ the MSR instruction.
+
+ * arm-dis.c (print_insn_arm): Decode _x and _s bits of the
+ field_mask of an MSR instruction.
+
2000-05-11 Thomas de Lellis <tdel@windriver.com>
* arm-opc.c: Disassembly of thumb ldsb/ldsh
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index f131ada..a3e7112 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -420,7 +420,7 @@ print_insn_arm (pc, info, given)
break;
case 'C':
- switch (given & 0x00090000)
+ switch (given & 0x000f0000)
{
default:
func (stream, "_???");
@@ -429,10 +429,16 @@ print_insn_arm (pc, info, given)
func (stream, "_all");
break;
case 0x10000:
- func (stream, "_ctl");
+ func (stream, "_c");
+ break;
+ case 0x20000:
+ func (stream, "_x");
+ break;
+ case 0x40000:
+ func (stream, "_s");
break;
case 0x80000:
- func (stream, "_flg");
+ func (stream, "_f");
break;
}
break;
diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h
index 8beb65f..5ecde4b 100644
--- a/opcodes/arm-opc.h
+++ b/opcodes/arm-opc.h
@@ -1,6 +1,6 @@
/* Opcode table for the ARM.
- Copyright 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 1996, 1997, 2000 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -93,8 +93,8 @@ static struct arm_opcode arm_opcodes[] =
{0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
{0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
{0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
- {0x0120f000, 0x0db6f000, "msr%c\t%22?scpsr%C, %o"},
- {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?scpsr"},
+ {0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
+ {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
{0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
{0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
{0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
@@ -164,7 +164,7 @@ static struct arm_opcode arm_opcodes[] =
{0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
{0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
-
+
/* The rest. */
{0x00000000, 0x00000000, "undefined instruction %0-31x"},
{0x00000000, 0x00000000, 0}