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| author | Jan Beulich <jbeulich@suse.com> | 2024-02-23 11:58:15 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-02-23 11:58:15 +0100 |
| commit | 2f630f60b5d91b83cbfd6c3ffc33da065bca2fa7 (patch) | |
| tree | 281a2fdaaaf68599bd464c1b355c96339ed6559b /opcodes | |
| parent | c429c4459865284a0059cbabdde0449eb7df0774 (diff) | |
| download | gdb-2f630f60b5d91b83cbfd6c3ffc33da065bca2fa7.zip gdb-2f630f60b5d91b83cbfd6c3ffc33da065bca2fa7.tar.gz gdb-2f630f60b5d91b83cbfd6c3ffc33da065bca2fa7.tar.bz2 | |
x86/APX: INV{EPT,PCID,VPID} are WIG
While various other entries in version 003 of the spec aren't quite as
explicit (due to simply leaving the respective field blank), all three
have a clear IGNORED there. IOW they ought to be emitted with EVEX.W=0
by default (and respect -mevexwig=).
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/i386-opc.tbl | 6 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 214e9fb..a709e7a 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1402,16 +1402,16 @@ getsec, 0xf37, SMX, NoSuf, {} invept, 0x660f3880, EPT&No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } invept, 0x660f3880, EPT&x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } -invept, 0xf3f0, EPT&APX_F, Modrm|NoSuf|EVexMap4, { Oword|Unspecified|BaseIndex, Reg64 } +invept, 0xf3f0, EPT&APX_F, Modrm|NoSuf|EVexMap4|VexWIG, { Oword|Unspecified|BaseIndex, Reg64 } invvpid, 0x660f3881, EPT&No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } invvpid, 0x660f3881, EPT&x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } -invvpid, 0xf3f1, EPT&APX_F, Modrm|NoSuf|EVexMap4, { Oword|Unspecified|BaseIndex, Reg64 } +invvpid, 0xf3f1, EPT&APX_F, Modrm|NoSuf|EVexMap4|VexWIG, { Oword|Unspecified|BaseIndex, Reg64 } // INVPCID instruction invpcid, 0x660f3882, INVPCID&No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } invpcid, 0x660f3882, INVPCID&x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } -invpcid, 0xf3f2, INVPCID&APX_F, Modrm|NoSuf|EVexMap4, { Oword|Unspecified|BaseIndex, Reg64 } +invpcid, 0xf3f2, INVPCID&APX_F, Modrm|NoSuf|EVexMap4|VexWIG, { Oword|Unspecified|BaseIndex, Reg64 } // SSSE3 instructions. diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 57e5959..0a51346 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -12796,7 +12796,7 @@ static const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0 } } } }, { MN_invept, 0xf0, 2, SPACE_EVEXMAP4, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 3, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 50, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, @@ -12826,7 +12826,7 @@ static const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0 } } } }, { MN_invvpid, 0xf1, 2, SPACE_EVEXMAP4, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 3, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 50, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, @@ -12856,7 +12856,7 @@ static const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0 } } } }, { MN_invpcid, 0xf2, 2, SPACE_EVEXMAP4, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 3, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 57, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, |