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| author | Jan Beulich <jbeulich@suse.com> | 2023-11-24 10:15:59 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-11-24 10:15:59 +0100 |
| commit | 2ec31e54dff83130fbde8d2f674469078ee203d5 (patch) | |
| tree | a4da2d3aa88727a4c69acd022a9b9a8edca7a7fa /opcodes | |
| parent | d3b01414b935be5c5d5f37e5df6b6767e9c68d25 (diff) | |
| download | gdb-2ec31e54dff83130fbde8d2f674469078ee203d5.zip gdb-2ec31e54dff83130fbde8d2f674469078ee203d5.tar.gz gdb-2ec31e54dff83130fbde8d2f674469078ee203d5.tar.bz2 | |
RISC-V: drop leftover match_never() references
Commit 27b33966b18e "RISC-V: disallow x0 with certain macro-insns"
wasn't properly re-based over recent opcode table additions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index c9ba4c9..bf19978 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2667,10 +2667,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vmsltu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS }, {"th.vmsge.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS }, {"th.vmsgeu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS }, -{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO }, -{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO }, -{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 1, (int) M_VMSGE, match_never, INSN_MACRO }, -{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, match_never, INSN_MACRO }, +{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 0, (int) M_VMSGE, NULL, INSN_MACRO }, +{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, NULL, INSN_MACRO }, +{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 1, (int) M_VMSGE, NULL, INSN_MACRO }, +{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, NULL, INSN_MACRO }, {"th.vminu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0}, {"th.vminu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0}, {"th.vmin.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0}, |