RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0

SiFive has define as set of flexible instruction for extending vector
coprocessor, it able to encoding opcode like .insn but with predefined
format.

List of instructions:
  sf.vc.x
  sf.vc.i
  sf.vc.vv
  sf.vc.xv
  sf.vc.iv
  sf.vc.fv
  sf.vc.vvv
  sf.vc.xvv
  sf.vc.ivv
  sf.vc.fvv
  sf.vc.vvw
  sf.vc.xvw
  sf.vc.ivw
  sf.vc.fvw
  sf.vc.v.x
  sf.vc.v.i
  sf.vc.v.vv
  sf.vc.v.xv
  sf.vc.v.iv
  sf.vc.v.fv
  sf.vc.v.vvv
  sf.vc.v.xvv
  sf.vc.v.ivv
  sf.vc.v.fvv
  sf.vc.v.vvw
  sf.vc.v.xvw
  sf.vc.v.ivw
  sf.vc.v.fvw

Spec of Xsfvcp
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software

Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>

2 files changed, 57 insertions, 0 deletions

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index f7f4c07..cb521dc 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -702,6 +702,33 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		    goto undefined_modifier;
 		}
 	      break;
+	    case 's': /* Vendor-specific (SiFive) operands.  */
+	      switch (*++oparg)
+		{
+		/* SiFive vector coprocessor interface.  */
+		case 'd':
+		  print (info->stream, dis_style_register, "0x%x",
+			 (unsigned) EXTRACT_OPERAND (RD, l));
+		  break;
+		case 't':
+		  print (info->stream, dis_style_register, "0x%x",
+			 (unsigned) EXTRACT_OPERAND (RS2, l));
+		  break;
+		case 'O':
+		  switch (*++oparg)
+		    {
+		    case '2':
+		      print (info->stream, dis_style_register, "0x%x",
+			     (unsigned) EXTRACT_OPERAND (XSO2, l));
+		      break;
+		    case '1':
+		      print (info->stream, dis_style_register, "0x%x",
+			     (unsigned) EXTRACT_OPERAND (XSO1, l));
+		      break;
+		    }
+		  break;
+		}
+	      break;
 	    default:
 	      goto undefined_modifier;
 	    }
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 011fd2e..24afb36 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2899,6 +2899,36 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
 {"vt.maskcn",  64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
 
+/* Vendor-specific (SiFive) vector coprocessor interface instructions.  */
+{"sf.vc.x",     0, INSN_CLASS_XSFVCP, "XsO2,Xst,Xsd,s",  MATCH_SF_VC_X, MASK_SF_VC_X, match_opcode, 0 },
+{"sf.vc.v.x",   0, INSN_CLASS_XSFVCP, "XsO2,Xst,Vd,s",  MATCH_SF_VC_V_X, MASK_SF_VC_V_X, match_opcode, 0 },
+{"sf.vc.i",     0, INSN_CLASS_XSFVCP, "XsO2,Xst,Xsd,Vi", MATCH_SF_VC_I, MASK_SF_VC_I, match_opcode, 0 },
+{"sf.vc.v.i",   0, INSN_CLASS_XSFVCP, "XsO2,Xst,Vd,Vi", MATCH_SF_VC_V_I, MASK_SF_VC_V_I, match_opcode, 0 },
+{"sf.vc.vv",    0, INSN_CLASS_XSFVCP, "XsO2,Xsd,Vt,Vs", MATCH_SF_VC_VV, MASK_SF_VC_VV, match_opcode, 0 },
+{"sf.vc.v.vv",  0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_V_VV, MASK_SF_VC_V_VV, match_opcode, 0 },
+{"sf.vc.xv",    0, INSN_CLASS_XSFVCP, "XsO2,Xsd,Vt,s",  MATCH_SF_VC_XV, MASK_SF_VC_XV, match_opcode, 0 },
+{"sf.vc.v.xv",  0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_V_XV, MASK_SF_VC_V_XV, match_opcode, 0 },
+{"sf.vc.iv",    0, INSN_CLASS_XSFVCP, "XsO2,Xsd,Vt,Vi", MATCH_SF_VC_IV, MASK_SF_VC_IV, match_opcode, 0 },
+{"sf.vc.v.iv",  0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_V_IV, MASK_SF_VC_V_IV, match_opcode, 0 },
+{"sf.vc.fv",    0, INSN_CLASS_XSFVCP, "XsO1,Xsd,Vt,S",  MATCH_SF_VC_FV, MASK_SF_VC_FV, match_opcode, 0 },
+{"sf.vc.v.fv",  0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FV, MASK_SF_VC_V_FV, match_opcode, 0 },
+{"sf.vc.vvv",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_VVV, MASK_SF_VC_VVV, match_opcode, 0 },
+{"sf.vc.v.vvv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_V_VVV, MASK_SF_VC_V_VVV, match_opcode, 0 },
+{"sf.vc.xvv",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_XVV, MASK_SF_VC_XVV, match_opcode, 0 },
+{"sf.vc.v.xvv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_V_XVV, MASK_SF_VC_V_XVV, match_opcode, 0 },
+{"sf.vc.ivv",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_IVV, MASK_SF_VC_IVV, match_opcode, 0 },
+{"sf.vc.v.ivv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_V_IVV, MASK_SF_VC_V_IVV, match_opcode, 0 },
+{"sf.vc.fvv",   0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_FVV, MASK_SF_VC_FVV, match_opcode, 0 },
+{"sf.vc.v.fvv", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FVV, MASK_SF_VC_V_FVV, match_opcode, 0 },
+{"sf.vc.vvw",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_VVW, MASK_SF_VC_VVW, match_opcode, 0 },
+{"sf.vc.v.vvw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_V_VVW, MASK_SF_VC_V_VVW, match_opcode, 0 },
+{"sf.vc.xvw",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_XVW, MASK_SF_VC_XVW, match_opcode, 0 },
+{"sf.vc.v.xvw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_V_XVW, MASK_SF_VC_V_XVW, match_opcode, 0 },
+{"sf.vc.ivw",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_IVW, MASK_SF_VC_IVW, match_opcode, 0 },
+{"sf.vc.v.ivw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_V_IVW, MASK_SF_VC_V_IVW, match_opcode, 0 },
+{"sf.vc.fvw",   0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 },
+{"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 },
+
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
 };