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authorJan Beulich <jbeulich@suse.com>2023-12-01 08:26:36 +0100
committerJan Beulich <jbeulich@suse.com>2023-12-01 08:26:36 +0100
commit1f865bae65db9588f6994c02a92355bfb4e3d955 (patch)
tree09535aa56d24787842ef624d8c7fb25c0bdd19a7 /opcodes
parenta521809d9b182d2863e2b0cf69270d1cef1da507 (diff)
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x86: allow 32-bit reg to be used with U{RD,WR}MSR
... as MSR index specifier: It is unreasonable to demand that people write less readable / understandable code, just because the present documentation mentions only Reg64. Whether to also adjust the disassembler is a separate question, perhaps indeed more tightly tied to what the spec says.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/i386-opc.tbl4
-rw-r--r--opcodes/i386-tbl.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b170d70..f89c4cb 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3359,9 +3359,9 @@ eretu, 0xf30f01ca, FRED, NoSuf, {}
// USER_MSR instructions.
-urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg64, Reg64 }
+urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg32|Reg64, Reg64 }
urdmsr, 0xf2f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }
-uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 }
+uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg32|Reg64 }
// Immediates want to be first; md_assemble() takes care of swapping operands
// accordingly.
uwrmsr, 0xf3f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e321535..eb25f20 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -39638,7 +39638,7 @@ static const insn_template i386_optab[] =
0 },
{ { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+ { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
@@ -39660,7 +39660,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
- { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_uwrmsr, 0xf8, 2, SPACE_VEXMAP7, 0,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,