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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-08-27 13:07:34 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-10-14 05:21:41 +0000 |
| commit | 1469f944d1d3f6c0f94c15716fdb74f9240a5136 (patch) | |
| tree | 524d181c952a15b5341fd094ef6176c9e2eb6553 /opcodes | |
| parent | 2b8fd83908ea61d9fb2215de5eb585870658fa89 (diff) | |
| download | gdb-1469f944d1d3f6c0f94c15716fdb74f9240a5136.zip gdb-1469f944d1d3f6c0f94c15716fdb74f9240a5136.tar.gz gdb-1469f944d1d3f6c0f94c15716fdb74f9240a5136.tar.bz2 | |
opcodes/riscv-dis.c: Tidying with spacing
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
This commit takes care of improper spacing for code clarity.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Tidying with spacing.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-dis.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 2d1faf2..088d0d9 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -715,7 +715,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) } /* If arch has the Zfinx extension, replace FPR with GPR. */ - if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) + if (riscv_subset_supports (&riscv_rps_dis, "zfinx")) riscv_fpr_names = riscv_gpr_names; for (; op->name; op++) |