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authorJan Beulich <jbeulich@novell.com>2017-02-22 10:36:05 +0100
committerJan Beulich <jbeulich@suse.com>2017-02-22 10:36:05 +0100
commit11648de5a91658326748dea1e4965559e9bd7a0f (patch)
tree05b442b83d62420bff0d88e0d2febafa9100f42d /opcodes
parente025ae68802a7cf217254c13e314f01247f74404 (diff)
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aarch64: actually copy first operand in convert_bfc_to_bfm()
Commit 93562a343c ("[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudo") changed the destination operand to 0, making the whole function invocation a no-op. We really want to copy operand 0 (a register) to operand 1 (an immediate before coming here), even if right now this likely is only a latent bug.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/aarch64-asm.c4
2 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8830698..234b58b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-02-21 Jan Beulich <jbeulich@suse.com>
+
+ * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
+ 1 (instead of to itself). Correct typo.
+
2017-02-14 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 398af8a..47d56f9 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1607,10 +1607,10 @@ convert_bfc_to_bfm (aarch64_inst *inst)
/* Insert XZR. */
copy_operand_info (inst, 3, 2);
copy_operand_info (inst, 2, 1);
- copy_operand_info (inst, 0, 0);
+ copy_operand_info (inst, 1, 0);
inst->operands[1].reg.regno = 0x1f;
- /* Convert the immedate operand. */
+ /* Convert the immediate operand. */
lsb = inst->operands[2].imm.value;
width = inst->operands[3].imm.value;
if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)