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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 11:04:32 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:39:29 +0100 |
| commit | 104fefeebb544b7745bb353b63110afa46119647 (patch) | |
| tree | 64540070841260d12abe4b232e89eb208ac77869 /opcodes | |
| parent | a97330e723cf3c639a951329ac5fe2797528249b (diff) | |
| download | gdb-104fefeebb544b7745bb353b63110afa46119647.zip gdb-104fefeebb544b7745bb353b63110afa46119647.tar.gz gdb-104fefeebb544b7745bb353b63110afa46119647.tar.bz2 | |
[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds support for the mitigation for Spectre Variant 4 by
adding the PSTATE bit SSBS which are accessible using MSR and MRS
instructions. Although this is a mandatory addition to the ARMv8.5-A,
it is permitted to be added to any version of the ARMv8 architecture.
This is enabled using the command line option of +ssbs for older
versions.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Add
SSBS in the check for one-bit immediate.
(aarch64_sys_regs): New entry for SSBS.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for SSBS.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "ssbs".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/ssbs-illegal1.d: New test.
* testsuite/gas/aarch64/ssbs-illegal1.l: New test.
* testsuite/gas/aarch64/ssbs-illegal2.d: New test.
* testsuite/gas/aarch64/ssbs-illegal2.l: New test.
* testsuite/gas/aarch64/ssbs.s: New test.
* testsuite/gas/aarch64/ssbs1.d: Test with +ssbs
* testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 14 |
2 files changed, 23 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 776aa0f..c234524 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,14 @@ 2018-10-09 Sudakshina Das <sudi.das@arm.com> + * aarch64-opc.c (operand_general_constraint_met_p): Add + SSBS in the check for one-bit immediate. + (aarch64_sys_regs): New entry for SSBS. + (aarch64_sys_reg_supported_p): New check for above. + (aarch64_pstatefields): New entry for SSBS. + (aarch64_pstatefield_supported_p): New check for above. + +2018-10-09 Sudakshina Das <sudi.das@arm.com> + * aarch64-opc.c (aarch64_sys_regs): New entries for scxtnum_el[0,1,2,3,12] and id_pfr2_el1. (aarch64_sys_reg_supported_p): New checks for above. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 4cf39d2..5cd57d5 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -2490,9 +2490,11 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4); /* MSR UAO, #uimm4 MSR PAN, #uimm4 + MSR SSBS,#uimm4 The immediate must be #0 or #1. */ if ((opnd->pstatefield == 0x03 /* UAO. */ || opnd->pstatefield == 0x04 /* PAN. */ + || opnd->pstatefield == 0x19 /* SSBS. */ || opnd->pstatefield == 0x1a) /* DIT. */ && opnds[1].imm.value > 1) { @@ -3708,6 +3710,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "pan", CPEN_(0,C2,3), F_ARCHEXT }, { "uao", CPEN_ (0, C2, 4), F_ARCHEXT }, { "nzcv", CPEN_(3,C2,0), 0 }, + { "ssbs", CPEN_(3,C2,6), F_ARCHEXT }, { "fpcr", CPEN_(3,C4,0), 0 }, { "fpsr", CPEN_(3,C4,1), 0 }, { "dspsr_el0", CPEN_(3,C5,0), 0 }, @@ -4128,6 +4131,11 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features, && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2)) return FALSE; + /* SSBS. Values are from aarch64_sys_regs. */ + if (reg->value == CPEN_(3,C2,6) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS)) + return FALSE; + /* Virtualization host extensions: system registers. */ if ((reg->value == CPENC (3, 4, C2, C0, 1) || reg->value == CPENC (3, 4, C13, C0, 1) @@ -4340,6 +4348,7 @@ const aarch64_sys_reg aarch64_pstatefields [] = { "daifclr", 0x1f, 0 }, { "pan", 0x04, F_ARCHEXT }, { "uao", 0x03, F_ARCHEXT }, + { "ssbs", 0x19, F_ARCHEXT }, { "dit", 0x1a, F_ARCHEXT }, { 0, CPENC(0,0,0,0,0), 0 }, }; @@ -4361,6 +4370,11 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features, && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) return FALSE; + /* SSBS. Values are from aarch64_pstatefields. */ + if (reg->value == 0x19 + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS)) + return FALSE; + /* DIT. Values are from aarch64_pstatefields. */ if (reg->value == 0x1a && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4)) |