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| author | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:16:44 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:16:44 +0100 |
| commit | 5437a02abc9fe106054965828787e8f232692935 (patch) | |
| tree | 4723e3eddeef436e20d15d44c109b0f1529db3ba /opcodes/xc16x-opc.c | |
| parent | 567dfba2bed4bce68a13b0c8963dec9605dea6c8 (diff) | |
| download | gdb-5437a02abc9fe106054965828787e8f232692935.zip gdb-5437a02abc9fe106054965828787e8f232692935.tar.gz gdb-5437a02abc9fe106054965828787e8f232692935.tar.bz2 | |
Arm64: correct address index operands for LD1RO{H,W,D}
Just like their LD1RQ{H,W,D} counterparts, as per the specification the
index registers get scaled by element size.
Diffstat (limited to 'opcodes/xc16x-opc.c')
0 files changed, 0 insertions, 0 deletions