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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-05-20 20:51:49 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-05-20 22:21:30 +0800 |
| commit | aa8c9d60a6fc8865a5c4131aab243bf97b961e2c (patch) | |
| tree | 3b19354c999a0b2be87240673c027e9cfcb5925f /opcodes/riscv-opc.c | |
| parent | f270fd72f6694daa74cbd4d42a1ed3aaeddb8e38 (diff) | |
| download | gdb-aa8c9d60a6fc8865a5c4131aab243bf97b961e2c.zip gdb-aa8c9d60a6fc8865a5c4131aab243bf97b961e2c.tar.gz gdb-aa8c9d60a6fc8865a5c4131aab243bf97b961e2c.tar.bz2 | |
RISC-V: Remove RV128-only fmv instructions
As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only),
it should be removed until RV128 support for GNU Binutils is required
again.
gas/ChangeLog:
* testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q,
MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.
Diffstat (limited to 'opcodes/riscv-opc.c')
| -rw-r--r-- | opcodes/riscv-opc.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 7524be7..eaba3cb 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -825,8 +825,6 @@ const struct riscv_opcode riscv_opcodes[] = {"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, {"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, {"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 }, -{"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 }, {"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, {"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, {"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, |