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| author | Ilya Tocar <ilya.tocar@intel.com> | 2014-02-20 19:08:13 +0400 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2014-02-25 08:52:02 -0800 |
| commit | d6e9dd78c4ac29900ed0047f15892720c67dff6b (patch) | |
| tree | ab6f626070cb50d86c92494b9da2cb4ad552bf15 /opcodes/i386-opc.tbl | |
| parent | 475109d8708bdc9c9a4667c0e460a1c395fdd8fd (diff) | |
| download | gdb-d6e9dd78c4ac29900ed0047f15892720c67dff6b.zip gdb-d6e9dd78c4ac29900ed0047f15892720c67dff6b.tar.gz gdb-d6e9dd78c4ac29900ed0047f15892720c67dff6b.tar.bz2 | |
Remove bogus vcvtps2ph variant.
We currently support version of vcvtps2ph with sae and only 1 register operand.
This version is encoded as if missing operand was equal to ymm0.
I didn't found any references to this variant in
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
This patch removes it.
opcodes/
* i386-opc.tbl: Remove wrong variant of vcvtps2ph
* i386-tbl.h: Regenerate.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e0b7072..b22ecad 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3633,7 +3633,6 @@ vcvtps2pd, 3, 0x5A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|RegMem } vcvtps2ph, 4, 0x661D, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegYMM|RegMem } vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 } -vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM|RegMem } vcvtsd2si, 2, 0xF22D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, Reg32 } vcvtsd2si, 3, 0xF22D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32 } |