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author | Jan Beulich <jbeulich@suse.com> | 2022-11-30 09:06:33 +0100 |
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committer | Jan Beulich <jbeulich@suse.com> | 2022-11-30 09:06:33 +0100 |
commit | ac9226cf8c496b15e369b2fcae95066f4a597a5b (patch) | |
tree | ee5644700ceb123597f406bfc9a09dbf29a7ca62 /opcodes/i386-opc.tbl | |
parent | 3df781c5a459249fcb49e20ee36bdcd7bf111f0c (diff) | |
download | gdb-ac9226cf8c496b15e369b2fcae95066f4a597a5b.zip gdb-ac9226cf8c496b15e369b2fcae95066f4a597a5b.tar.gz gdb-ac9226cf8c496b15e369b2fcae95066f4a597a5b.tar.bz2 |
x86: drop FloatR
There are just 4 templates using it, which can be easily identified by
other means, as D is set only on a very limited number of FPU templates.
Also move the respective conditional out of the code path taken by all
"reverse match" insns (it probably should have been this way already
before, to avoid the one conditional in the common case).
With this the templates which had FloatR dropped no longer differ from
their AT&T syntax + mnemonic counterparts - the only difference is now
which of the two would be recognized. For this, however, we don't need
two templates - we can simply arrange the condition for setting
Opcode_FloatR accordingly.
Diffstat (limited to 'opcodes/i386-opc.tbl')
-rw-r--r-- | opcodes/i386-opc.tbl | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e59ad8f..41e3f99 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -694,11 +694,10 @@ faddp, 0xdec0, None, CpuFP, NoSuf|Ugh, { FloatReg, FloatAcc } // subtract fsub, 0xd8e0, None, CpuFP, NoSuf, { FloatReg } -fsub, 0xd8e0, None, CpuFP, D|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } +fsub, 0xd8e0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } // alias for fsubp fsub, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} fsub, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fsub, 0xd8e0, None, CpuFP, NoSuf|D|FloatR, { FloatReg, FloatAcc } fsub, 0xd8, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } fisub, 0xde, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } @@ -711,11 +710,10 @@ fsubp, 0xdee9, None, CpuFP, NoSuf, {} // subtract reverse fsubr, 0xd8e8, None, CpuFP, NoSuf, { FloatReg } -fsubr, 0xd8e8, None, CpuFP, D|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } +fsubr, 0xd8e8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } // alias for fsubrp fsubr, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} fsubr, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fsubr, 0xd8e8, None, CpuFP, NoSuf|D|FloatR, { FloatReg, FloatAcc } fsubr, 0xd8, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } fisubr, 0xde, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } @@ -741,11 +739,10 @@ fmulp, 0xdec8, None, CpuFP, NoSuf|Ugh, { FloatReg, FloatAcc } // divide fdiv, 0xd8f0, None, CpuFP, NoSuf, { FloatReg } -fdiv, 0xd8f0, None, CpuFP, D|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } +fdiv, 0xd8f0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } // alias for fdivp fdiv, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} fdiv, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fdiv, 0xd8f0, None, CpuFP, NoSuf|D|FloatR, { FloatReg, FloatAcc } fdiv, 0xd8, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } fidiv, 0xde, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } @@ -758,11 +755,10 @@ fdivp, 0xdef9, None, CpuFP, NoSuf, {} // divide reverse fdivr, 0xd8f8, None, CpuFP, NoSuf, { FloatReg } -fdivr, 0xd8f8, None, CpuFP, D|NoSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } +fdivr, 0xd8f8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } // alias for fdivrp fdivr, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} fdivr, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fdivr, 0xd8f8, None, CpuFP, NoSuf|D|FloatR, { FloatReg, FloatAcc } fdivr, 0xd8, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } fidivr, 0xde, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } |