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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-01 13:44:45 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-07 20:38:11 +0000 |
| commit | 9203a155ee9722be40d48fbd970c9e8ce3355dff (patch) | |
| tree | 2733f2a84e2838e42c57796ddba141cd9005fcf4 /opcodes/aarch64-sys-regs.def | |
| parent | 8c3273ee07fae4badfd6f25f67162e5f6ec7f03e (diff) | |
| download | gdb-9203a155ee9722be40d48fbd970c9e8ce3355dff.zip gdb-9203a155ee9722be40d48fbd970c9e8ce3355dff.tar.gz gdb-9203a155ee9722be40d48fbd970c9e8ce3355dff.tar.bz2 | |
aarch64: Add THE system register support
Add Binutils support for system registers associated with the
Translation Hardening Extension (THE).
In doing so, we also add core feature support for THE, enabling its
associated feature flag and implementing the necessary
feature-checking machinery.
Regression tested on aarch64-linux-gnu, no regressions.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_features): Add "+the" feature modifier.
* doc/c-aarch64.texi (AArch64 Extensions): Update
documentation for `the' option.
* testsuite/gas/aarch64/sysreg-8.s: Add tests for `the'
associated system registers.
* testsuite/gas/aarch64/sysreg-8.d: Likewise.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_feature_bit): Add
AARCH64_FEATURE_THE.
opcode/ChangeLog:
* aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Add `the'
system register check support.
* aarch64-sys-regs.def: Add `rcwmask_el1' and `rcwsmask_el1'
* aarch64-tbl.h: Define `THE' preprocessor macro.
Diffstat (limited to 'opcodes/aarch64-sys-regs.def')
| -rw-r--r-- | opcodes/aarch64-sys-regs.def | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 2f5780a..dc43126 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -756,6 +756,8 @@ SYSREG ("prlar_el2", CPENC (3,4,6,8,1), F_ARCHEXT, AARCH64_FEATURE (V8R)) SYSREG ("prselr_el1", CPENC (3,0,6,2,1), F_ARCHEXT, AARCH64_FEATURE (V8R)) SYSREG ("prselr_el2", CPENC (3,4,6,2,1), F_ARCHEXT, AARCH64_FEATURE (V8R)) + SYSREG ("rcwmask_el1", CPENC (3,0,13,0,6), F_ARCHEXT, AARCH64_FEATURE (THE)) + SYSREG ("rcwsmask_el1", CPENC (3,0,13,0,3), F_ARCHEXT, AARCH64_FEATURE (THE)) SYSREG ("revidr_el1", CPENC (3,0,0,0,6), F_REG_READ, AARCH64_NO_FEATURES) SYSREG ("rgsr_el1", CPENC (3,0,1,0,5), F_ARCHEXT, AARCH64_FEATURE (MEMTAG)) SYSREG ("rmr_el1", CPENC (3,0,12,0,2), 0, AARCH64_NO_FEATURES) |