diff options
| -rw-r--r-- | gas/config/tc-aarch64.c | 1 | ||||
| -rw-r--r-- | gas/doc/c-aarch64.texi | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-8.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-8.s | 5 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-sys-regs.def | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 3 |
8 files changed, 25 insertions, 0 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 1f687fe..c6566e1 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10285,6 +10285,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"cssc", AARCH64_FEATURE (CSSC), AARCH64_NO_FEATURES}, {"chk", AARCH64_FEATURE (CHK), AARCH64_NO_FEATURES}, {"gcs", AARCH64_FEATURE (GCS), AARCH64_NO_FEATURES}, + {"the", AARCH64_FEATURE (THE), AARCH64_NO_FEATURES}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index a3ca714..8af38f2 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -263,6 +263,9 @@ automatically cause those extensions to be disabled. @tab Enable Check Feature Status Extension. @item @code{gcs} @tab N/A @tab No @tab Enable Guarded Control Stack Extension. +@item @code{the} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later + @tab Enable Translation Hardening extension. + @end multitable @node AArch64 Syntax diff --git a/gas/testsuite/gas/aarch64/sysreg-8.d b/gas/testsuite/gas/aarch64/sysreg-8.d index 3be4120..09b6724 100644 --- a/gas/testsuite/gas/aarch64/sysreg-8.d +++ b/gas/testsuite/gas/aarch64/sysreg-8.d @@ -289,3 +289,7 @@ Disassembly of section \.text: [^:]*: d5189923 msr pmsnevfr_el1, x3 [^:]*: d53c1242 mrs x2, hcrx_el2 [^:]*: d51c1243 msr hcrx_el2, x3 +[^:]*: d538d0c2 mrs x2, rcwmask_el1 +[^:]*: d518d0c3 msr rcwmask_el1, x3 +[^:]*: d538d062 mrs x2, rcwsmask_el1 +[^:]*: d518d063 msr rcwsmask_el1, x3 diff --git a/gas/testsuite/gas/aarch64/sysreg-8.s b/gas/testsuite/gas/aarch64/sysreg-8.s index 8ce36c7..21daa8c 100644 --- a/gas/testsuite/gas/aarch64/sysreg-8.s +++ b/gas/testsuite/gas/aarch64/sysreg-8.s @@ -185,3 +185,8 @@ rwreg pmsnevfr_el1 rwreg hcrx_el2 + + .arch armv8-a+the + + rwreg rcwmask_el1 + rwreg rcwsmask_el1 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 72d8ec2..c081760 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -165,6 +165,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_GCS, /* SME2. */ AARCH64_FEATURE_SME2, + /* Translation Hardening Extension. */ + AARCH64_FEATURE_THE, AARCH64_NUM_FEATURES }; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 6d9f3a0..336a49f 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -5032,6 +5032,11 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features, && AARCH64_CPU_HAS_FEATURE (features, PREDRES)) return true; + if ((reg_value == CPENC (3,0,13,0,3) + || CPENC (3,0,13,0,6)) + && AARCH64_CPU_HAS_FEATURE (features, THE)) + return true; + return false; } diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 2f5780a..dc43126 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -756,6 +756,8 @@ SYSREG ("prlar_el2", CPENC (3,4,6,8,1), F_ARCHEXT, AARCH64_FEATURE (V8R)) SYSREG ("prselr_el1", CPENC (3,0,6,2,1), F_ARCHEXT, AARCH64_FEATURE (V8R)) SYSREG ("prselr_el2", CPENC (3,4,6,2,1), F_ARCHEXT, AARCH64_FEATURE (V8R)) + SYSREG ("rcwmask_el1", CPENC (3,0,13,0,6), F_ARCHEXT, AARCH64_FEATURE (THE)) + SYSREG ("rcwsmask_el1", CPENC (3,0,13,0,3), F_ARCHEXT, AARCH64_FEATURE (THE)) SYSREG ("revidr_el1", CPENC (3,0,0,0,6), F_REG_READ, AARCH64_NO_FEATURES) SYSREG ("rgsr_el1", CPENC (3,0,1,0,5), F_ARCHEXT, AARCH64_FEATURE (MEMTAG)) SYSREG ("rmr_el1", CPENC (3,0,12,0,2), 0, AARCH64_NO_FEATURES) diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 463939d..e624b85 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2576,6 +2576,8 @@ static const aarch64_feature_set aarch64_feature_chk = AARCH64_FEATURE (CHK); static const aarch64_feature_set aarch64_feature_gcs = AARCH64_FEATURE (GCS); +static const aarch64_feature_set aarch64_feature_the = + AARCH64_FEATURE (THE); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2636,6 +2638,7 @@ static const aarch64_feature_set aarch64_feature_gcs = #define CSSC &aarch64_feature_cssc #define CHK &aarch64_feature_chk #define GCS &aarch64_feature_gcs +#define THE &aarch64_feature_the #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } |