Align .TOC. for PowerPC64

This change, with prerequisite 0e5fabeb, provides a toc base aligned
to 256 bytes rather than 8 bytes.  This is necessary for a minor gcc
optimisation, allowing use of d-form instructions to correctly access
toc-relative items larger than 8 bytes.

bfd/
	* elf64-ppc.c (TOC_BASE_ALIGN): Define.
	(ppc64_elf_next_toc_section): Align multi-got toc base.
	(ppc64_elf_set_toc): Likewise initial toc base and .TOC. symbol.
ld/
	* emulparams/elf64ppc.sh (GOT): Align.
ld/testsuite/
	* ld-powerpc/ambiguousv1b.d: Update for aligned .got.
	* ld-powerpc/defsym.d: Likewise.
	* ld-powerpc/elfv2-2exe.d: Likewise.
	* ld-powerpc/elfv2exe.d: Likewise.
	* ld-powerpc/elfv2so.d: Likewise.
	* ld-powerpc/relbrlt.d: Likewise.
	* ld-powerpc/tls.g: Likewise.
	* ld-powerpc/tlsexe.d: Likewise.
	* ld-powerpc/tlsexe.g: Likewise.
	* ld-powerpc/tlsexe.r: Likewise.
	* ld-powerpc/tlsexetoc.d: Likewise.
	* ld-powerpc/tlsexetoc.g: Likewise.
	* ld-powerpc/tlsexetoc.r: Likewise.
	* ld-powerpc/tlsso.d: Likewise.
	* ld-powerpc/tlsso.g: Likewise.
	* ld-powerpc/tlsso.r: Likewise.
	* ld-powerpc/tlstoc.g: Likewise.
	* ld-powerpc/tlstocso.d: Likewise.
	* ld-powerpc/tlstocso.g: Likewise.
	* ld-powerpc/tlstocso.r: Likewise.
	* ld-powerpc/tocopt.d: Likewise.
	* ld-powerpc/tocopt2.d: Likewise.
	* ld-powerpc/tocopt3.d: Likewise.
	* ld-powerpc/tocopt4.d: Likewise.
	* ld-powerpc/tocopt5.d: Likewise.

26 files changed, 159 insertions, 131 deletions

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 8c37da2..71c74fb 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,31 @@
+2015-04-23  Alan Modra  <amodra@gmail.com>
+
+	* ld-powerpc/ambiguousv1b.d: Update for aligned .got.
+	* ld-powerpc/defsym.d: Likewise.
+	* ld-powerpc/elfv2-2exe.d: Likewise.
+	* ld-powerpc/elfv2exe.d: Likewise.
+	* ld-powerpc/elfv2so.d: Likewise.
+	* ld-powerpc/relbrlt.d: Likewise.
+	* ld-powerpc/tls.g: Likewise.
+	* ld-powerpc/tlsexe.d: Likewise.
+	* ld-powerpc/tlsexe.g: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexetoc.d: Likewise.
+	* ld-powerpc/tlsexetoc.g: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.d: Likewise.
+	* ld-powerpc/tlsso.g: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlstoc.g: Likewise.
+	* ld-powerpc/tlstocso.d: Likewise.
+	* ld-powerpc/tlstocso.g: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+	* ld-powerpc/tocopt.d: Likewise.
+	* ld-powerpc/tocopt2.d: Likewise.
+	* ld-powerpc/tocopt3.d: Likewise.
+	* ld-powerpc/tocopt4.d: Likewise.
+	* ld-powerpc/tocopt5.d: Likewise.
+
 2015-04-22  Alan Modra  <amodra@gmail.com>
 
 	* ld-x86-64/pr18176.d: Update.
diff --git a/ld/testsuite/ld-powerpc/ambiguousv1b.d b/ld/testsuite/ld-powerpc/ambiguousv1b.d
index b20ad9f..7b9753a 100644
--- a/ld/testsuite/ld-powerpc/ambiguousv1b.d
+++ b/ld/testsuite/ld-powerpc/ambiguousv1b.d
@@ -16,9 +16,9 @@ Relocation section .* contains 1 entries:
 Symbol table '\.dynsym' contains 5 entries:
 .*
      0: .*
-     1: 0+10010390     4 FUNC    GLOBAL DEFAULT   12 my_func
+     1: 0+10010408     4 FUNC    GLOBAL DEFAULT   12 my_func
 #...
 Symbol table '\.symtab' contains 20 entries:
 #...
-    15: 0+10010390     4 FUNC    GLOBAL DEFAULT   12 my_func
+    15: 0+10010408     4 FUNC    GLOBAL DEFAULT   12 my_func
 #pass
diff --git a/ld/testsuite/ld-powerpc/defsym.d b/ld/testsuite/ld-powerpc/defsym.d
index 1e5b567..adff02b 100644
--- a/ld/testsuite/ld-powerpc/defsym.d
+++ b/ld/testsuite/ld-powerpc/defsym.d
@@ -8,19 +8,19 @@
 Disassembly of section \.text:
 
 0+100000b0 <_start>:
-    100000b0:	(15 00 00 48|48 00 00 15) 	bl      100000c4 <(foo|bar)\+0x8>
-    100000b4:	(11 00 00 48|48 00 00 11) 	bl      100000c4 <(foo|bar)\+0x8>
-    100000b8:	(00 00 00 60|60 00 00 00) 	nop
+    100000b0:	(48 00 00 15|15 00 00 48) 	bl      100000c4 <(foo|bar)\+0x8>
+    100000b4:	(48 00 00 11|11 00 00 48) 	bl      100000c4 <(foo|bar)\+0x8>
+    100000b8:	(60 00 00 00|00 00 00 60) 	nop
 
 0+100000bc <(foo|bar)>:
-    100000bc:	(02 10 40 3c|3c 40 10 02) 	lis     r2,4098
-    100000c0:	(c8 80 42 38|38 42 80 c8) 	addi    r2,r2,-32568
-    100000c4:	(20 00 80 4e|4e 80 00 20) 	blr
+    100000bc:	(3c 40 10 02|02 10 40 3c) 	lis     r2,4098
+    100000c0:	(38 42 80 00|00 80 42 38) 	addi    r2,r2,-32768
+    100000c4:	(4e 80 00 20|20 00 80 4e) 	blr
 
 Disassembly of section \.data:
 
 0+100100c8 .*:
-    100100c8:	(bc 00 00 10|00 00 00 00) 	.*
-    100100cc:	(00 00 00 00|10 00 00 bc) 	.*
-    100100d0:	(bc 00 00 10|00 00 00 00) 	.*
-    100100d4:	(00 00 00 00|10 00 00 bc) 	.*
+    100100c8:	(00 00 00 00|bc 00 00 10) 	.*
+    100100cc:	(10 00 00 bc|00 00 00 00) 	.*
+    100100d0:	(00 00 00 00|bc 00 00 10) 	.*
+    100100d4:	(10 00 00 bc|00 00 00 00) 	.*
diff --git a/ld/testsuite/ld-powerpc/elfv2-2exe.d b/ld/testsuite/ld-powerpc/elfv2-2exe.d
index c8deda1..e1787d1 100644
--- a/ld/testsuite/ld-powerpc/elfv2-2exe.d
+++ b/ld/testsuite/ld-powerpc/elfv2-2exe.d
@@ -10,10 +10,10 @@ Disassembly of section \.text:
 
 0+10000078 <f1>:
 .*:	(3c 40 10 01|01 10 40 3c) 	lis     r2,4097
-.*:	(38 42 80 78|78 80 42 38) 	addi    r2,r2,-32648
+.*:	(38 42 80 00|00 80 42 38) 	addi    r2,r2,-32768
 .*:	(4e 80 00 20|20 00 80 4e) 	blr
 0+10000084 <f2>:
-.*:	(38 4c 7f f4|f4 7f 4c 38) 	addi    r2,r12,32756
+.*:	(38 4c 7f 7c|7c 7f 4c 38) 	addi    r2,r12,32636
 .*:	(4e 80 00 20|20 00 80 4e) 	blr
 .*:	(00 00 00 00|78 00 00 10) .*
 .*:	(10 00 00 78|00 00 00 00) .*
@@ -34,7 +34,7 @@ Disassembly of section \.text:
 
 0+100000cc <f3>:
 .*:	(3c 40 10 01|01 10 40 3c) 	lis     r2,4097
-.*:	(38 42 80 78|78 80 42 38) 	addi    r2,r2,-32648
+.*:	(38 42 80 00|00 80 42 38) 	addi    r2,r2,-32768
 .*:	(4e 80 00 20|20 00 80 4e) 	blr
 
 0+100000d8 <f4>:
diff --git a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d
index 78d3727..3447c37 100644
--- a/ld/testsuite/ld-powerpc/elfv2exe.d
+++ b/ld/testsuite/ld-powerpc/elfv2exe.d
@@ -8,33 +8,33 @@
 Disassembly of section \.text:
 
 0+100000c0 <.*\.plt_branch\.f2>:
-.*:	(ff ff 82 3d|3d 82 ff ff) 	addis   r12,r2,-1
-.*:	(f0 7f 8c e9|e9 8c 7f f0) 	ld      r12,32752\(r12\)
-.*:	(a6 03 89 7d|7d 89 03 a6) 	mtctr   r12
-.*:	(20 04 80 4e|4e 80 04 20) 	bctr
+.*:	(3d 82 ff ff|ff ff 82 3d) 	addis   r12,r2,-1
+.*:	(e9 8c 7f 28|28 7f 8c e9) 	ld      r12,32552\(r12\)
+.*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
+.*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
 0+100000d0 <.*\.plt_branch\.f4>:
-.*:	(ff ff 82 3d|3d 82 ff ff) 	addis   r12,r2,-1
-.*:	(f8 7f 8c e9|e9 8c 7f f8) 	ld      r12,32760\(r12\)
-.*:	(a6 03 89 7d|7d 89 03 a6) 	mtctr   r12
-.*:	(20 04 80 4e|4e 80 04 20) 	bctr
+.*:	(3d 82 ff ff|ff ff 82 3d) 	addis   r12,r2,-1
+.*:	(e9 8c 7f 30|30 7f 8c e9) 	ld      r12,32560\(r12\)
+.*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
+.*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
 0+100000e0 <_start>:
-.*:	(02 10 40 3c|3c 40 10 02) 	lis     r2,4098
-.*:	(38 81 42 38|38 42 81 38) 	addi    r2,r2,-32456
-.*:	(a6 02 08 7c|7c 08 02 a6) 	mflr    r0
-.*:	(e1 ff 21 f8|f8 21 ff e1) 	stdu    r1,-32\(r1\)
-.*:	(30 00 01 f8|f8 01 00 30) 	std     r0,48\(r1\)
-.*:	(f5 ff ff 4b|4b ff ff f5) 	bl      .* <_start\+0x8>
-.*:	(08 80 62 e8|e8 62 80 08) 	ld      r3,-32760\(r2\)
-.*:	(c5 ff ff 4b|4b ff ff c5) 	bl      .*\.plt_branch\.f2>
-.*:	(00 00 00 60|60 00 00 00) 	nop
-.*:	(10 80 62 e8|e8 62 80 10) 	ld      r3,-32752\(r2\)
-.*:	(81 87 00 48|48 00 87 81) 	bl      10008888 <f3>
-.*:	(00 00 00 60|60 00 00 00) 	nop
-.*:	(c1 ff ff 4b|4b ff ff c1) 	bl      .*\.plt_branch\.f4>
-.*:	(00 00 00 60|60 00 00 00) 	nop
-.*:	(30 00 01 e8|e8 01 00 30) 	ld      r0,48\(r1\)
-.*:	(20 00 21 38|38 21 00 20) 	addi    r1,r1,32
-.*:	(a6 03 08 7c|7c 08 03 a6) 	mtlr    r0
-.*:	(20 00 80 4e|4e 80 00 20) 	blr
+.*:	(3c 40 10 02|02 10 40 3c) 	lis     r2,4098
+.*:	(38 42 82 00|00 82 42 38) 	addi    r2,r2,-32256
+.*:	(7c 08 02 a6|a6 02 08 7c) 	mflr    r0
+.*:	(f8 21 ff e1|e1 ff 21 f8) 	stdu    r1,-32\(r1\)
+.*:	(f8 01 00 30|30 00 01 f8) 	std     r0,48\(r1\)
+.*:	(4b ff ff f5|f5 ff ff 4b) 	bl      .* <_start\+0x8>
+.*:	(e8 62 80 08|08 80 62 e8) 	ld      r3,-32760\(r2\)
+.*:	(4b ff ff c5|c5 ff ff 4b) 	bl      .*\.plt_branch\.f2>
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(e8 62 80 10|10 80 62 e8) 	ld      r3,-32752\(r2\)
+.*:	(48 00 87 81|81 87 00 48) 	bl      10008888 <f3>
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(4b ff ff c1|c1 ff ff 4b) 	bl      .*\.plt_branch\.f4>
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(e8 01 00 30|30 00 01 e8) 	ld      r0,48\(r1\)
+.*:	(38 21 00 20|20 00 21 38) 	addi    r1,r1,32
+.*:	(7c 08 03 a6|a6 03 08 7c) 	mtlr    r0
+.*:	(4e 80 00 20|20 00 80 4e) 	blr
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d
index 28cfdb0..906b375 100644
--- a/ld/testsuite/ld-powerpc/elfv2so.d
+++ b/ld/testsuite/ld-powerpc/elfv2so.d
@@ -8,75 +8,75 @@
 Disassembly of section \.text:
 
 0+320 <.*\.plt_call\.f4>:
-.*:	(18 00 41 f8|f8 41 00 18) 	std     r2,24\(r1\)
-.*:	(38 80 82 e9|e9 82 80 38) 	ld      r12,-32712\(r2\)
-.*:	(a6 03 89 7d|7d 89 03 a6) 	mtctr   r12
-.*:	(20 04 80 4e|4e 80 04 20) 	bctr
+.*:	(f8 41 00 18|18 00 41 f8) 	std     r2,24\(r1\)
+.*:	(e9 82 80 38|38 80 82 e9) 	ld      r12,-32712\(r2\)
+.*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
+.*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
 0+330 <.*\.plt_call\.f3>:
-.*:	(18 00 41 f8|f8 41 00 18) 	std     r2,24\(r1\)
-.*:	(28 80 82 e9|e9 82 80 28) 	ld      r12,-32728\(r2\)
-.*:	(a6 03 89 7d|7d 89 03 a6) 	mtctr   r12
-.*:	(20 04 80 4e|4e 80 04 20) 	bctr
+.*:	(f8 41 00 18|18 00 41 f8) 	std     r2,24\(r1\)
+.*:	(e9 82 80 28|28 80 82 e9) 	ld      r12,-32728\(r2\)
+.*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
+.*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
 0+340 <.*\.plt_call\.f2>:
-.*:	(18 00 41 f8|f8 41 00 18) 	std     r2,24\(r1\)
-.*:	(30 80 82 e9|e9 82 80 30) 	ld      r12,-32720\(r2\)
-.*:	(a6 03 89 7d|7d 89 03 a6) 	mtctr   r12
-.*:	(20 04 80 4e|4e 80 04 20) 	bctr
+.*:	(f8 41 00 18|18 00 41 f8) 	std     r2,24\(r1\)
+.*:	(e9 82 80 30|30 80 82 e9) 	ld      r12,-32720\(r2\)
+.*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
+.*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
 0+350 <.*\.plt_call\.f1>:
-.*:	(18 00 41 f8|f8 41 00 18) 	std     r2,24\(r1\)
-.*:	(40 80 82 e9|e9 82 80 40) 	ld      r12,-32704\(r2\)
-.*:	(a6 03 89 7d|7d 89 03 a6) 	mtctr   r12
-.*:	(20 04 80 4e|4e 80 04 20) 	bctr
+.*:	(f8 41 00 18|18 00 41 f8) 	std     r2,24\(r1\)
+.*:	(e9 82 80 40|40 80 82 e9) 	ld      r12,-32704\(r2\)
+.*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
+.*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
 0+360 <f1>:
-.*:	(02 00 4c 3c|3c 4c 00 02) 	addis   r2,r12,2
-.*:	(d8 81 42 38|38 42 81 d8) 	addi    r2,r2,-32296
-.*:	(a6 02 08 7c|7c 08 02 a6) 	mflr    r0
-.*:	(e1 ff 21 f8|f8 21 ff e1) 	stdu    r1,-32\(r1\)
-.*:	(30 00 01 f8|f8 01 00 30) 	std     r0,48\(r1\)
-.*:	(dd ff ff 4b|4b ff ff dd) 	bl      .*\.plt_call\.f1>
-.*:	(08 80 62 e8|e8 62 80 08) 	ld      r3,-32760\(r2\)
-.*:	(c5 ff ff 4b|4b ff ff c5) 	bl      .*\.plt_call\.f2>
-.*:	(18 00 41 e8|e8 41 00 18) 	ld      r2,24\(r1\)
-.*:	(10 80 62 e8|e8 62 80 10) 	ld      r3,-32752\(r2\)
-.*:	(a9 ff ff 4b|4b ff ff a9) 	bl      .*\.plt_call\.f3>
-.*:	(18 00 41 e8|e8 41 00 18) 	ld      r2,24\(r1\)
-.*:	(91 ff ff 4b|4b ff ff 91) 	bl      .*\.plt_call\.f4>
-.*:	(18 00 41 e8|e8 41 00 18) 	ld      r2,24\(r1\)
-.*:	(30 00 01 e8|e8 01 00 30) 	ld      r0,48\(r1\)
-.*:	(20 00 21 38|38 21 00 20) 	addi    r1,r1,32
-.*:	(a6 03 08 7c|7c 08 03 a6) 	mtlr    r0
-.*:	(20 00 80 4e|4e 80 00 20) 	blr
-.*:	(98 01 01 00|00 00 00 00) 	.*
-.*:	(00 00 00 00|00 01 01 98) 	.*
+.*:	(3c 4c 00 02|02 00 4c 3c) 	addis   r2,r12,2
+.*:	(38 42 82 a0|a0 82 42 38) 	addi    r2,r2,-32096
+.*:	(7c 08 02 a6|a6 02 08 7c) 	mflr    r0
+.*:	(f8 21 ff e1|e1 ff 21 f8) 	stdu    r1,-32\(r1\)
+.*:	(f8 01 00 30|30 00 01 f8) 	std     r0,48\(r1\)
+.*:	(4b ff ff dd|dd ff ff 4b) 	bl      .*\.plt_call\.f1>
+.*:	(e8 62 80 08|08 80 62 e8) 	ld      r3,-32760\(r2\)
+.*:	(4b ff ff c5|c5 ff ff 4b) 	bl      .*\.plt_call\.f2>
+.*:	(e8 41 00 18|18 00 41 e8) 	ld      r2,24\(r1\)
+.*:	(e8 62 80 10|10 80 62 e8) 	ld      r3,-32752\(r2\)
+.*:	(4b ff ff a9|a9 ff ff 4b) 	bl      .*\.plt_call\.f3>
+.*:	(e8 41 00 18|18 00 41 e8) 	ld      r2,24\(r1\)
+.*:	(4b ff ff 91|91 ff ff 4b) 	bl      .*\.plt_call\.f4>
+.*:	(e8 41 00 18|18 00 41 e8) 	ld      r2,24\(r1\)
+.*:	(e8 01 00 30|30 00 01 e8) 	ld      r0,48\(r1\)
+.*:	(38 21 00 20|20 00 21 38) 	addi    r1,r1,32
+.*:	(7c 08 03 a6|a6 03 08 7c) 	mtlr    r0
+.*:	(4e 80 00 20|20 00 80 4e) 	blr
+.*:	(00 00 00 00|60 02 01 00) 	.*
+.*:	(00 01 02 60|00 00 00 00) 	.*
 
 0+3b0 <__glink_PLTresolve>:
-.*:	(a6 02 08 7c|7c 08 02 a6) 	mflr    r0
-.*:	(05 00 9f 42|42 9f 00 05) 	bcl     .*
-.*:	(a6 02 68 7d|7d 68 02 a6) 	mflr    r11
-.*:	(f0 ff 4b e8|e8 4b ff f0) 	ld      r2,-16\(r11\)
-.*:	(a6 03 08 7c|7c 08 03 a6) 	mtlr    r0
-.*:	(50 60 8b 7d|7d 8b 60 50) 	subf    r12,r11,r12
-.*:	(14 5a 62 7d|7d 62 5a 14) 	add     r11,r2,r11
-.*:	(d0 ff 0c 38|38 0c ff d0) 	addi    r0,r12,-48
-.*:	(00 00 8b e9|e9 8b 00 00) 	ld      r12,0\(r11\)
-.*:	(82 f0 00 78|78 00 f0 82) 	rldicl  r0,r0,62,2
-.*:	(a6 03 89 7d|7d 89 03 a6) 	mtctr   r12
-.*:	(08 00 6b e9|e9 6b 00 08) 	ld      r11,8\(r11\)
-.*:	(20 04 80 4e|4e 80 04 20) 	bctr
-.*:	(00 00 00 60|60 00 00 00) 	nop
+.*:	(7c 08 02 a6|a6 02 08 7c) 	mflr    r0
+.*:	(42 9f 00 05|05 00 9f 42) 	bcl     .*
+.*:	(7d 68 02 a6|a6 02 68 7d) 	mflr    r11
+.*:	(e8 4b ff f0|f0 ff 4b e8) 	ld      r2,-16\(r11\)
+.*:	(7c 08 03 a6|a6 03 08 7c) 	mtlr    r0
+.*:	(7d 8b 60 50|50 60 8b 7d) 	subf    r12,r11,r12
+.*:	(7d 62 5a 14|14 5a 62 7d) 	add     r11,r2,r11
+.*:	(38 0c ff d0|d0 ff 0c 38) 	addi    r0,r12,-48
+.*:	(e9 8b 00 00|00 00 8b e9) 	ld      r12,0\(r11\)
+.*:	(78 00 f0 82|82 f0 00 78) 	rldicl  r0,r0,62,2
+.*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
+.*:	(e9 6b 00 08|08 00 6b e9) 	ld      r11,8\(r11\)
+.*:	(4e 80 04 20|20 04 80 4e) 	bctr
+.*:	(60 00 00 00|00 00 00 60) 	nop
 
 .* <f3@plt>:
-.*:	(c8 ff ff 4b|4b ff ff c8) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff c8|c8 ff ff 4b) 	b       .* <__glink_PLTresolve>
 
 .* <f2@plt>:
-.*:	(c4 ff ff 4b|4b ff ff c4) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff c4|c4 ff ff 4b) 	b       .* <__glink_PLTresolve>
 
 .* <f4@plt>:
-.*:	(c0 ff ff 4b|4b ff ff c0) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff c0|c0 ff ff 4b) 	b       .* <__glink_PLTresolve>
 
 .* <f1@plt>:
-.*:	(bc ff ff 4b|4b ff ff bc) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff bc|bc ff ff 4b) 	b       .* <__glink_PLTresolve>
diff --git a/ld/testsuite/ld-powerpc/relbrlt.d b/ld/testsuite/ld-powerpc/relbrlt.d
index b04ae7d..a5f2437 100644
--- a/ld/testsuite/ld-powerpc/relbrlt.d
+++ b/ld/testsuite/ld-powerpc/relbrlt.d
@@ -22,7 +22,7 @@ Disassembly of section \.text:
 	\.\.\.
 
 [0-9a-f	 ]*<.*plt_branch.*>:
-[0-9a-f	 ]*:	(e9 82 80 00|00 80 82 e9) 	ld      r12,-32768\(r2\)
+[0-9a-f	 ]*:	(e9 82 80 e8|e8 80 82 e9) 	ld      r12,-32536\(r2\)
 [0-9a-f	 ]*: R_PPC64_TOC16_DS	\*ABS\*\+0x157f00e8
 [0-9a-f	 ]*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 [0-9a-f	 ]*:	(4e 80 04 20|20 04 80 4e) 	bctr
@@ -32,7 +32,7 @@ Disassembly of section \.text:
 [0-9a-f	 ]*: R_PPC64_REL24	\*ABS\*\+0x137e00fc
 
 [0-9a-f	 ]*<.*plt_branch.*>:
-[0-9a-f	 ]*:	(e9 82 80 08|08 80 82 e9) 	ld      r12,-32760\(r2\)
+[0-9a-f	 ]*:	(e9 82 80 f0|f0 80 82 e9) 	ld      r12,-32528\(r2\)
 [0-9a-f	 ]*: R_PPC64_TOC16_DS	\*ABS\*\+0x157f00f0
 [0-9a-f	 ]*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 [0-9a-f	 ]*:	(4e 80 04 20|20 04 80 4e) 	bctr
diff --git a/ld/testsuite/ld-powerpc/tls.g b/ld/testsuite/ld-powerpc/tls.g
index d4910ca..140872b 100644
--- a/ld/testsuite/ld-powerpc/tls.g
+++ b/ld/testsuite/ld-powerpc/tls.g
@@ -8,5 +8,5 @@
 .*
 
 Contents of section \.got:
- 100101f8 (00000000|f8810110) (100181f8|00000000) (ffffffff|1880ffff) (ffff8018|ffffffff)  .*
- 10010208 (ffffffff|5880ffff) (ffff8058|ffffffff)                    .*
+ 10010200 (00000000|00820110) (10018200|00000000) (ffffffff|1880ffff) (ffff8018|ffffffff)  .*
+.* (ffffffff|5880ffff) (ffff8058|ffffffff)                    .*
diff --git a/ld/testsuite/ld-powerpc/tlsexe.d b/ld/testsuite/ld-powerpc/tlsexe.d
index 7aa1c6d..5a449f7 100644
--- a/ld/testsuite/ld-powerpc/tlsexe.d
+++ b/ld/testsuite/ld-powerpc/tlsexe.d
@@ -67,8 +67,8 @@ Disassembly of section \.text:
 .*	(e9 4d 90 2a|2a 90 4d e9) 	lwa     r10,-28632\(r13\)
 .*	(3d 2d 00 00|00 00 2d 3d) 	addis   r9,r13,0
 .*	(a9 49 90 30|30 90 49 a9) 	lha     r10,-28624\(r9\)
-.*	(00 00 00 00|18 02 01 00) .*
-.*	(00 01 02 18|00 00 00 00) .*
+.*	(00 00 00 00|e0 02 01 00) .*
+.*	(00 01 02 e0|00 00 00 00) .*
 .* <__glink_PLTresolve>:
 .*	(7d 88 02 a6|a6 02 88 7d) 	mflr    r12
 .*	(42 9f 00 05|05 00 9f 42) 	bcl     20,4\*cr7\+so,.*
diff --git a/ld/testsuite/ld-powerpc/tlsexe.g b/ld/testsuite/ld-powerpc/tlsexe.g
index fb8dbb3..8c15244 100644
--- a/ld/testsuite/ld-powerpc/tlsexe.g
+++ b/ld/testsuite/ld-powerpc/tlsexe.g
@@ -7,6 +7,6 @@
 .*
 
 Contents of section \.got:
-.* (00000000|38860110) (10018638|00000000) (ffffffff|1880ffff) (ffff8018|ffffffff)  .*
+ 10010700 (00000000|00870110) (10018700|00000000) (ffffffff|1880ffff) (ffff8018|ffffffff)  .*
 .* 00000000 00000000 00000000 00000000  .*
 .* 00000000 00000000 00000000 00000000  .*
diff --git a/ld/testsuite/ld-powerpc/tlsexe.r b/ld/testsuite/ld-powerpc/tlsexe.r
index 94e5272..db72ad7 100644
--- a/ld/testsuite/ld-powerpc/tlsexe.r
+++ b/ld/testsuite/ld-powerpc/tlsexe.r
@@ -21,7 +21,7 @@ Section Headers:
  +\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
  +\[[ 0-9]+\] \.dynamic +DYNAMIC .* 0+160 10 +WA +4 +0 +8
  +\[[ 0-9]+\] \.opd .*
- +\[[ 0-9]+\] \.got +PROGBITS .* 0+30 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] \.got +PROGBITS .* 0+30 08 +WA +0 +0 +256
  +\[[ 0-9]+\] \.plt +.*
  +\[[ 0-9]+\] \.shstrtab +.*
  +\[[ 0-9]+\] \.symtab +.*
diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.d b/ld/testsuite/ld-powerpc/tlsexetoc.d
index d478167..1c70d54 100644
--- a/ld/testsuite/ld-powerpc/tlsexetoc.d
+++ b/ld/testsuite/ld-powerpc/tlsexetoc.d
@@ -51,8 +51,8 @@ Disassembly of section \.text:
 .*	(89 4d 90 60|60 90 4d 89) 	lbz     r10,-28576\(r13\)
 .*	(3d 2d 00 00|00 00 2d 3d) 	addis   r9,r13,0
 .*	(99 49 90 68|68 90 49 99) 	stb     r10,-28568\(r9\)
-.*	(00 00 00 00|40 02 01 00) .*
-.*	(00 01 02 40|00 00 00 00) .*
+.*	(00 00 00 00|68 02 01 00) .*
+.*	(00 01 02 68|00 00 00 00) .*
 .* <__glink_PLTresolve>:
 .*	(7d 88 02 a6|a6 02 88 7d) 	mflr    r12
 .*	(42 9f 00 05|05 00 9f 42) 	bcl     20,4\*cr7\+so,.*
diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.g b/ld/testsuite/ld-powerpc/tlsexetoc.g
index b75c8e6..14a0477 100644
--- a/ld/testsuite/ld-powerpc/tlsexetoc.g
+++ b/ld/testsuite/ld-powerpc/tlsexetoc.g
@@ -7,7 +7,7 @@
 .*
 
 Contents of section \.got:
-.* (00000000|d8850110) (100185d8|00000000) 00000000 00000000  .*
+ 10010600 (00000000|00860110) (10018600|00000000) 00000000 00000000  .*
 .* 00000000 00000000 00000000 00000000  .*
 .* 00000000 00000000 (00000000|01000000) (00000001|00000000)  .*
 .* 00000000 00000000 (00000000|01000000) (00000001|00000000)  .*
diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.r b/ld/testsuite/ld-powerpc/tlsexetoc.r
index 7b55281..56716bb 100644
--- a/ld/testsuite/ld-powerpc/tlsexetoc.r
+++ b/ld/testsuite/ld-powerpc/tlsexetoc.r
@@ -21,7 +21,7 @@ Section Headers:
  +\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
  +\[[ 0-9]+\] \.dynamic +DYNAMIC .* 0+160 10 +WA +4 +0 +8
  +\[[ 0-9]+\] \.opd .*
- +\[[ 0-9]+\] \.got +PROGBITS .* 0+58 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] \.got +PROGBITS .* 0+58 08 +WA +0 +0 +256
  +\[[ 0-9]+\] \.plt +.*
  +\[[ 0-9]+\] \.shstrtab +.*
  +\[[ 0-9]+\] \.symtab +.*
diff --git a/ld/testsuite/ld-powerpc/tlsso.d b/ld/testsuite/ld-powerpc/tlsso.d
index 7fe7e87..8ac25e6 100644
--- a/ld/testsuite/ld-powerpc/tlsso.d
+++ b/ld/testsuite/ld-powerpc/tlsso.d
@@ -57,8 +57,8 @@ Disassembly of section \.text:
 .*	(3d 2d 00 00|00 00 2d 3d) 	addis   r9,r13,0
 .*	(a9 49 00 00|00 00 49 a9) 	lha     r10,0\(r9\)
 .*	(60 00 00 00|00 00 00 60) 	nop
-.*	(00 00 00 00|38 02 01 00) .*
-.*	(00 01 02 38|00 00 00 00) .*
+.*	(00 00 00 00|58 02 01 00) .*
+.*	(00 01 02 58|00 00 00 00) .*
 .* <__glink_PLTresolve>:
 .*	(7d 88 02 a6|a6 02 88 7d) 	mflr    r12
 .*	(42 9f 00 05|05 00 9f 42) 	bcl     20,4\*cr7\+so,.*
diff --git a/ld/testsuite/ld-powerpc/tlsso.g b/ld/testsuite/ld-powerpc/tlsso.g
index 0ba9fda..f8ac949 100644
--- a/ld/testsuite/ld-powerpc/tlsso.g
+++ b/ld/testsuite/ld-powerpc/tlsso.g
@@ -7,7 +7,7 @@
 .*
 
 Contents of section \.got:
- 107e0 (00000000|e0870100) (000187e0|00000000) 00000000 00000000  .*
+ 10800 (00000000|00880100) (00018800|00000000) 00000000 00000000  .*
 .* 00000000 00000000 00000000 00000000  .*
 .* 00000000 00000000 00000000 00000000  .*
 .* 00000000 00000000 00000000 00000000  .*
diff --git a/ld/testsuite/ld-powerpc/tlsso.r b/ld/testsuite/ld-powerpc/tlsso.r
index e0a3a75..fd3002b 100644
--- a/ld/testsuite/ld-powerpc/tlsso.r
+++ b/ld/testsuite/ld-powerpc/tlsso.r
@@ -47,7 +47,7 @@ Program Headers:
 Relocation section '\.rela\.dyn' at offset .* contains 18 entries:
  +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
 [0-9a-f ]+R_PPC64_RELATIVE +55c
-[0-9a-f ]+R_PPC64_RELATIVE +187e0
+[0-9a-f ]+R_PPC64_RELATIVE +18800
 [0-9a-f ]+R_PPC64_TPREL16 +0+60 le0 \+ 0
 [0-9a-f ]+R_PPC64_TPREL16_HA +0+68 le1 \+ 0
 [0-9a-f ]+R_PPC64_TPREL16_LO +0+68 le1 \+ 0
diff --git a/ld/testsuite/ld-powerpc/tlstoc.g b/ld/testsuite/ld-powerpc/tlstoc.g
index e5c1e31..bb97629 100644
--- a/ld/testsuite/ld-powerpc/tlstoc.g
+++ b/ld/testsuite/ld-powerpc/tlstoc.g
@@ -8,8 +8,8 @@
 .*
 
 Contents of section \.got:
- 100101b8 (00000000|01000000) (00000001|00000000) 00000000 00000000  .*
- 100101c8 (00000000|01000000) (00000001|00000000) 00000000 00000000  .*
- 100101d8 (00000000|01000000) (00000001|00000000) 00000000 00000000  .*
- 100101e8 (00000000|01000000) (00000001|00000000) 00000000 00000000  .*
- 100101f8 (ffffffff|6080ffff) (ffff8060|ffffffff) 00000000 00000000  .*
+ 10010200 (00000000|01000000) (00000001|00000000) 00000000 00000000  .*
+.* (00000000|01000000) (00000001|00000000) 00000000 00000000  .*
+.* (00000000|01000000) (00000001|00000000) 00000000 00000000  .*
+.* (00000000|01000000) (00000001|00000000) 00000000 00000000  .*
+.* (ffffffff|6080ffff) (ffff8060|ffffffff) 00000000 00000000  .*
diff --git a/ld/testsuite/ld-powerpc/tlstocso.d b/ld/testsuite/ld-powerpc/tlstocso.d
index 6aa1056..ad9481a 100644
--- a/ld/testsuite/ld-powerpc/tlstocso.d
+++ b/ld/testsuite/ld-powerpc/tlstocso.d
@@ -41,8 +41,8 @@ Disassembly of section \.text:
 .*	(3d 2d 00 00|00 00 2d 3d) 	addis   r9,r13,0
 .*	(99 49 00 00|00 00 49 99) 	stb     r10,0\(r9\)
 .*	(60 00 00 00|00 00 00 60) 	nop
-.*	(00 00 00 00|30 02 01 00) .*
-.*	(00 01 02 30|00 00 00 00) .*
+.*	(00 00 00 00|10 03 01 00) .*
+.*	(00 01 03 10|00 00 00 00) .*
 .* <__glink_PLTresolve>:
 .*	(7d 88 02 a6|a6 02 88 7d) 	mflr    r12
 .*	(42 9f 00 05|05 00 9f 42) 	bcl     20,4\*cr7\+so,.*
diff --git a/ld/testsuite/ld-powerpc/tlstocso.g b/ld/testsuite/ld-powerpc/tlstocso.g
index 9da93ec..2e5ffc8 100644
--- a/ld/testsuite/ld-powerpc/tlstocso.g
+++ b/ld/testsuite/ld-powerpc/tlstocso.g
@@ -7,7 +7,7 @@
 .*
 
 Contents of section \.got:
- 10720 (00000000|20870100) (00018720|00000000) 00000000 00000000  .*
+ 10800 (00000000|00880100) (00018800|00000000) 00000000 00000000  .*
 .* 00000000 00000000 00000000 00000000  .*
 .* 00000000 00000000 00000000 00000000  .*
 .* 00000000 00000000 00000000 00000000  .*
diff --git a/ld/testsuite/ld-powerpc/tlstocso.r b/ld/testsuite/ld-powerpc/tlstocso.r
index 0006db9..765bf08 100644
--- a/ld/testsuite/ld-powerpc/tlstocso.r
+++ b/ld/testsuite/ld-powerpc/tlstocso.r
@@ -47,7 +47,7 @@ Program Headers:
 Relocation section '\.rela\.dyn' at offset .* contains 13 entries:
  +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
 [0-9a-f ]+R_PPC64_RELATIVE +4dc
-[0-9a-f ]+R_PPC64_RELATIVE +18720
+[0-9a-f ]+R_PPC64_RELATIVE +18800
 [0-9a-f ]+R_PPC64_TPREL16 +0+60 le0 \+ 0
 [0-9a-f ]+R_PPC64_TPREL16_HA +0+68 le1 \+ 0
 [0-9a-f ]+R_PPC64_TPREL16_LO +0+68 le1 \+ 0
diff --git a/ld/testsuite/ld-powerpc/tocopt.d b/ld/testsuite/ld-powerpc/tocopt.d
index 161f00d..272f470 100644
--- a/ld/testsuite/ld-powerpc/tocopt.d
+++ b/ld/testsuite/ld-powerpc/tocopt.d
@@ -7,8 +7,8 @@ Contents of section \.text:
  100000d0 (3d220000|0000223d) (39298033|33802939) (3c820000|0000823c) (38a48008|0880a438)  .*
  100000e0 (e8c50000|0000c5e8) (3fa00000|0000a03f) (3bbd8010|1080bd3b) (7c62e82a|2ae8627c)  .*
 Contents of section \.got:
- 100100f0 (00000000|f0800110) (100180f0|00000000) (00000000|24010110) (10010124|00000000)  .*
- 10010100 (00000000|25010110) (10010125|00000000) (00000000|20010110) (10010120|00000000)  .*
- 10010110 (00000000|21010110) (10010121|00000000) (00000000|22010110) (10010122|00000000)  .*
+ 10010100 (00000000|00810110) (10018100|00000000) (00000000|34010110) (10010134|00000000)  .*
+ 10010110 (00000000|35010110) (10010135|00000000) (00000000|30010110) (10010130|00000000)  .*
+ 10010120 (00000000|31010110) (10010131|00000000) (00000000|32010110) (10010132|00000000)  .*
 Contents of section \.sdata:
- 10010120 01020304 0506                        .*
+ 10010130 01020304 0506                        .*
diff --git a/ld/testsuite/ld-powerpc/tocopt2.d b/ld/testsuite/ld-powerpc/tocopt2.d
index a3e4aa7..6850563 100644
--- a/ld/testsuite/ld-powerpc/tocopt2.d
+++ b/ld/testsuite/ld-powerpc/tocopt2.d
@@ -2,4 +2,4 @@
 .*:     file format .*
 
 Contents of section \.text:
- 100000b0 (3d22effe|feef223d) (39297f4a|4a7f2939) .*
+ 100000b0 (3d22effe|feef223d) (39297f02|027f2939) .*
diff --git a/ld/testsuite/ld-powerpc/tocopt3.d b/ld/testsuite/ld-powerpc/tocopt3.d
index a3e4aa7..6850563 100644
--- a/ld/testsuite/ld-powerpc/tocopt3.d
+++ b/ld/testsuite/ld-powerpc/tocopt3.d
@@ -2,4 +2,4 @@
 .*:     file format .*
 
 Contents of section \.text:
- 100000b0 (3d22effe|feef223d) (39297f4a|4a7f2939) .*
+ 100000b0 (3d22effe|feef223d) (39297f02|027f2939) .*
diff --git a/ld/testsuite/ld-powerpc/tocopt4.d b/ld/testsuite/ld-powerpc/tocopt4.d
index 1e0ccc5..7dbfc44 100644
--- a/ld/testsuite/ld-powerpc/tocopt4.d
+++ b/ld/testsuite/ld-powerpc/tocopt4.d
@@ -4,4 +4,4 @@
 Contents of section \.text:
  100000b0 (e9298000|008029e9) .*
 Contents of section \.got:
- 100100b8 (00000000|02000000) (00000002|00000000) .*
+ 10010100 (00000000|02000000) (00000002|00000000) .*
diff --git a/ld/testsuite/ld-powerpc/tocopt5.d b/ld/testsuite/ld-powerpc/tocopt5.d
index 758b7fc..1c93674 100644
--- a/ld/testsuite/ld-powerpc/tocopt5.d
+++ b/ld/testsuite/ld-powerpc/tocopt5.d
@@ -6,8 +6,8 @@ Contents of section \.text:
  100000c0 (e8c50000|0000c5e8) (60000000|00000060) (3922802b|2b802239) (60000000|00000060)  .*
  100000d0 (38a28008|0880a238) (e8c50000|0000c5e8)                    .*
 Contents of section \.got:
- 100100d8 (00000000|d8800110) (100180d8|00000000) (00000000|04010110) (10010104|00000000)  .*
- 100100e8 (00000000|05010110) (10010105|00000000) (00000000|00010110) (10010100|00000000)  .*
- 100100f8 (00000000|01010110) (10010101|00000000)                    .*
+ 10010100 (00000000|00810110) (10018100|00000000) (00000000|2c010110) (1001012c|00000000)  .*
+ 10010110 (00000000|2d010110) (1001012d|00000000) (00000000|28010110) (10010128|00000000)  .*
+ 10010120 (00000000|29010110) (10010129|00000000)                    .*
 Contents of section \.sdata:
- 10010100 01020304 0506                        .*
+ 10010128 01020304 0506                        .*