diff options
Diffstat (limited to 'ld/testsuite/ld-powerpc/elfv2exe.d')
| -rw-r--r-- | ld/testsuite/ld-powerpc/elfv2exe.d | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d index 78d3727..3447c37 100644 --- a/ld/testsuite/ld-powerpc/elfv2exe.d +++ b/ld/testsuite/ld-powerpc/elfv2exe.d @@ -8,33 +8,33 @@ Disassembly of section \.text: 0+100000c0 <.*\.plt_branch\.f2>: -.*: (ff ff 82 3d|3d 82 ff ff) addis r12,r2,-1 -.*: (f0 7f 8c e9|e9 8c 7f f0) ld r12,32752\(r12\) -.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 -.*: (20 04 80 4e|4e 80 04 20) bctr +.*: (3d 82 ff ff|ff ff 82 3d) addis r12,r2,-1 +.*: (e9 8c 7f 28|28 7f 8c e9) ld r12,32552\(r12\) +.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 +.*: (4e 80 04 20|20 04 80 4e) bctr 0+100000d0 <.*\.plt_branch\.f4>: -.*: (ff ff 82 3d|3d 82 ff ff) addis r12,r2,-1 -.*: (f8 7f 8c e9|e9 8c 7f f8) ld r12,32760\(r12\) -.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 -.*: (20 04 80 4e|4e 80 04 20) bctr +.*: (3d 82 ff ff|ff ff 82 3d) addis r12,r2,-1 +.*: (e9 8c 7f 30|30 7f 8c e9) ld r12,32560\(r12\) +.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 +.*: (4e 80 04 20|20 04 80 4e) bctr 0+100000e0 <_start>: -.*: (02 10 40 3c|3c 40 10 02) lis r2,4098 -.*: (38 81 42 38|38 42 81 38) addi r2,r2,-32456 -.*: (a6 02 08 7c|7c 08 02 a6) mflr r0 -.*: (e1 ff 21 f8|f8 21 ff e1) stdu r1,-32\(r1\) -.*: (30 00 01 f8|f8 01 00 30) std r0,48\(r1\) -.*: (f5 ff ff 4b|4b ff ff f5) bl .* <_start\+0x8> -.*: (08 80 62 e8|e8 62 80 08) ld r3,-32760\(r2\) -.*: (c5 ff ff 4b|4b ff ff c5) bl .*\.plt_branch\.f2> -.*: (00 00 00 60|60 00 00 00) nop -.*: (10 80 62 e8|e8 62 80 10) ld r3,-32752\(r2\) -.*: (81 87 00 48|48 00 87 81) bl 10008888 <f3> -.*: (00 00 00 60|60 00 00 00) nop -.*: (c1 ff ff 4b|4b ff ff c1) bl .*\.plt_branch\.f4> -.*: (00 00 00 60|60 00 00 00) nop -.*: (30 00 01 e8|e8 01 00 30) ld r0,48\(r1\) -.*: (20 00 21 38|38 21 00 20) addi r1,r1,32 -.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0 -.*: (20 00 80 4e|4e 80 00 20) blr +.*: (3c 40 10 02|02 10 40 3c) lis r2,4098 +.*: (38 42 82 00|00 82 42 38) addi r2,r2,-32256 +.*: (7c 08 02 a6|a6 02 08 7c) mflr r0 +.*: (f8 21 ff e1|e1 ff 21 f8) stdu r1,-32\(r1\) +.*: (f8 01 00 30|30 00 01 f8) std r0,48\(r1\) +.*: (4b ff ff f5|f5 ff ff 4b) bl .* <_start\+0x8> +.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\) +.*: (4b ff ff c5|c5 ff ff 4b) bl .*\.plt_branch\.f2> +.*: (60 00 00 00|00 00 00 60) nop +.*: (e8 62 80 10|10 80 62 e8) ld r3,-32752\(r2\) +.*: (48 00 87 81|81 87 00 48) bl 10008888 <f3> +.*: (60 00 00 00|00 00 00 60) nop +.*: (4b ff ff c1|c1 ff ff 4b) bl .*\.plt_branch\.f4> +.*: (60 00 00 00|00 00 00 60) nop +.*: (e8 01 00 30|30 00 01 e8) ld r0,48\(r1\) +.*: (38 21 00 20|20 00 21 38) addi r1,r1,32 +.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0 +.*: (4e 80 00 20|20 00 80 4e) blr |