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authorChristoph Müllner <christoph.muellner@vrull.eu>2022-06-28 17:44:57 +0200
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>2022-09-22 18:06:09 +0200
commitf511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20 (patch)
tree6958b2ab3024e997f728a7811ea0099a5f30df3f /include
parent4041e11db3ec3611921d10150572a92689aa3154 (diff)
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RISC-V: Add T-Head FMemIdx vendor extension
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadFMemIdx extension, a collection of T-Head-specific floating-point memory access instructions. The 'th' prefix and the "XTheadFMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include')
-rw-r--r--include/opcode/riscv-opc.h26
-rw-r--r--include/opcode/riscv.h1
2 files changed, 27 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index b504ce0..ecba9f5 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2186,6 +2186,23 @@
#define MASK_TH_MVEQZ 0xfe00707f
#define MATCH_TH_MVNEZ 0x4200100b
#define MASK_TH_MVNEZ 0xfe00707f
+/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */
+#define MATCH_TH_FLRD 0x6000600b
+#define MASK_TH_FLRD 0xf800707f
+#define MATCH_TH_FLRW 0x4000600b
+#define MASK_TH_FLRW 0xf800707f
+#define MATCH_TH_FLURD 0x7000600b
+#define MASK_TH_FLURD 0xf800707f
+#define MATCH_TH_FLURW 0x5000600b
+#define MASK_TH_FLURW 0xf800707f
+#define MATCH_TH_FSRD 0x6000700b
+#define MASK_TH_FSRD 0xf800707f
+#define MATCH_TH_FSRW 0x4000700b
+#define MASK_TH_FSRW 0xf800707f
+#define MATCH_TH_FSURD 0x7000700b
+#define MASK_TH_FSURD 0xf800707f
+#define MATCH_TH_FSURW 0x5000700b
+#define MASK_TH_FSURW 0xf800707f
/* Vendor-specific (T-Head) XTheadMac instructions. */
#define MATCH_TH_MULA 0x2000100b
#define MASK_TH_MULA 0xfe00707f
@@ -2988,6 +3005,15 @@ DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL)
/* Vendor-specific (T-Head) XTheadCondMov instructions. */
DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ)
DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ)
+/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */
+DECLARE_INSN(th_flrd, MATCH_TH_FLRD, MASK_TH_FLRD)
+DECLARE_INSN(th_flrw, MATCH_TH_FLRW, MASK_TH_FLRW)
+DECLARE_INSN(th_flurd, MATCH_TH_FLURD, MASK_TH_FLURD)
+DECLARE_INSN(th_flurw, MATCH_TH_FLURW, MASK_TH_FLURW)
+DECLARE_INSN(th_fsrd, MATCH_TH_FSRD, MASK_TH_FSRD)
+DECLARE_INSN(th_fsrw, MATCH_TH_FSRW, MASK_TH_FSRW)
+DECLARE_INSN(th_fsurd, MATCH_TH_FSURD, MASK_TH_FSURD)
+DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW)
/* Vendor-specific (T-Head) XTheadMac instructions. */
DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA)
DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 854269a..1b7de3c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -420,6 +420,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADBS,
INSN_CLASS_XTHEADCMO,
INSN_CLASS_XTHEADCONDMOV,
+ INSN_CLASS_XTHEADFMEMIDX,
INSN_CLASS_XTHEADMAC,
INSN_CLASS_XTHEADSYNC,
};