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authorNick Clifton <nickc@redhat.com>2008-02-27 12:33:43 +0000
committerNick Clifton <nickc@redhat.com>2008-02-27 12:33:43 +0000
commitaf7329f0ff70842d615f8af5fc3397d6892c8478 (patch)
tree2d4b4adf0d2afc765c8b9d88c6534393e7f45303 /include
parentb14f9da0aefde1e39bccd5f3daa437d06b4379d3 (diff)
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PR 3134
* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction with a 32-bit displacement but without the top bit of the 4th byte set. * gas/h8300/pr3134.s: New test. * gas/h8300/pr3134.d: Expected disassembly * gas/h8300/h8300.exp: Run the new test. * gas/h8300/h8300-coff.exp: Fix test for COFF based ports to accept h8300-rtemscoff not just h8300-rtems.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ChangeLog8
-rw-r--r--include/opcode/h8300.h3
2 files changed, 10 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 1de316e..1782853 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,11 @@
+2008-02-27 Markus Gyger <markus+sw@gyger.org>
+ Nick Clifton <nickc@redhat.com>
+
+ PR 3134
+ * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
+ with a 32-bit displacement but without the top bit of the 4th byte
+ set.
+
2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
* cr16.h (cr16_num_optab): Declared.
diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h
index 10fdf52..32e43c7 100644
--- a/include/opcode/h8300.h
+++ b/include/opcode/h8300.h
@@ -1,6 +1,6 @@
/* Opcode table for the H8/300
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002,
- 2003, 2004
+ 2003, 2004, 2008
Free Software Foundation, Inc.
Written by Steve Chamberlain <sac@cygnus.com>.
@@ -1519,6 +1519,7 @@ struct h8_opcode h8_opcodes[] =
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
+ {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},