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authorJ.T. Conklin <jtc@acorntoolworks.com>2000-05-03 22:19:45 +0000
committerJ.T. Conklin <jtc@acorntoolworks.com>2000-05-03 22:19:45 +0000
commit966f959b21353361298b03f5c69f2c906a3f307b (patch)
treedc2d70fd43f82a6692efeb6cb9ba1cec049cd88b /include
parent5ae3d4361a988e322cd9d17a6b044a037aef4273 (diff)
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* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
(PPC_OPERAND_VR): New operand flag for vector registers.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ChangeLog5
-rw-r--r--include/opcode/ppc.h8
2 files changed, 13 insertions, 0 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 5b1e41e..c47ded6 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2000-05-03 J.T. Conklin <jtc@redback.com>
+
+ * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
+ (PPC_OPERAND_VR): New operand flag for vector registers.
+
2000-05-01 Kazu Hirata <kazu@hxi.com>
* h8300.h (EOP): Add missing initializer.
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 974f0df..246e3c7 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -88,6 +88,9 @@ extern const int powerpc_num_opcodes;
/* Opcode is supported as part of the 64-bit bridge. */
#define PPC_OPCODE_64_BRIDGE (0400)
+/* Opcode is supported by Altivec Vector Unit */
+#define PPC_OPCODE_ALTIVEC (01000)
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
@@ -221,6 +224,11 @@ extern const struct powerpc_operand powerpc_operands[];
number is allowed). This flag will only be set for a signed
operand. */
#define PPC_OPERAND_NEGATIVE (04000)
+
+/* This operand names a vector unit register. The disassembler
+ prints these with a leading 'v'. */
+#define PPC_OPERAND_VR (010000)
+
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an