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authorChristoph Müllner <christoph.muellner@vrull.eu>2022-06-28 17:44:37 +0200
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>2022-09-22 18:06:09 +0200
commit73442230966a22b3238b2074691a71d7b4ed914a (patch)
tree973dd8274f6432ff4977d7e9174d4dd0b6467db4 /include
parent8254c3d2c94ae5458095ea6c25446ba89134b9da (diff)
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RISC-V: Add T-Head CondMov vendor extension
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadCondMov extension, a collection of T-Head-specific conditional move instructions. The 'th' prefix and the "XTheadCondMov" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include')
-rw-r--r--include/opcode/riscv-opc.h8
-rw-r--r--include/opcode/riscv.h1
2 files changed, 9 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9ed5cb4..5c0f610 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2181,6 +2181,11 @@
#define MASK_TH_L2CACHE_CIALL 0xffffffff
#define MATCH_TH_L2CACHE_IALL 0x0160000b
#define MASK_TH_L2CACHE_IALL 0xffffffff
+/* Vendor-specific (T-Head) XTheadCondMov instructions. */
+#define MATCH_TH_MVEQZ 0x4000100b
+#define MASK_TH_MVEQZ 0xfe00707f
+#define MATCH_TH_MVNEZ 0x4200100b
+#define MASK_TH_MVNEZ 0xfe00707f
/* Vendor-specific (T-Head) XTheadSync instructions. */
#define MATCH_TH_SFENCE_VMAS 0x0400000b
#define MASK_TH_SFENCE_VMAS 0xfe007fff
@@ -2967,6 +2972,9 @@ DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA)
DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL)
DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL)
DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL)
+/* Vendor-specific (T-Head) XTheadCondMov instructions. */
+DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ)
+DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ)
/* Vendor-specific (T-Head) XTheadSync instructions. */
DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS)
DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 53b5b3c..d0ff929 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -419,6 +419,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,
INSN_CLASS_XTHEADCMO,
+ INSN_CLASS_XTHEADCONDMOV,
INSN_CLASS_XTHEADSYNC,
};