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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-30 22:44:01 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:28:40 -0600 |
| commit | 5ec6edd0a215651c4d20984b48095941167e2c0a (patch) | |
| tree | 18c785a7b40b519e207980741229aec5c67975b1 /include | |
| parent | 62edb233ef5fff5356c46570b3ba19dcbe6ceb35 (diff) | |
| download | gdb-5ec6edd0a215651c4d20984b48095941167e2c0a.zip gdb-5ec6edd0a215651c4d20984b48095941167e2c0a.tar.gz gdb-5ec6edd0a215651c4d20984b48095941167e2c0a.tar.bz2 | |
RISC-V: Add support for the Zvksed ISA extension
Zvksed is part of the vector crypto extensions.
This extension adds the following instructions:
- vsm4k.vi
- vsm4r.[vv,vs]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvksed.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvksed.d: New test.
* testsuite/gas/riscv/zvksed.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSM4K_VI): New.
(MASK_VSM4K_VI): New.
(MATCH_VSM4R_VS): New.
(MASK_VSM4R_VS): New.
(MATCH_VSM4R_VV): New.
(MASK_VSM4R_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvksed.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvksed instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 11 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 12 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 95c4188..39c0cad 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2198,6 +2198,13 @@ #define MASK_VSHA2CL_VV 0xfe00707f #define MATCH_VSHA2MS_VV 0xb6002077 #define MASK_VSHA2MS_VV 0xfe00707f +/* Zvksed instructions. */ +#define MATCH_VSM4K_VI 0x86002077 +#define MASK_VSM4K_VI 0xfe00707f +#define MATCH_VSM4R_VS 0xa6082077 +#define MASK_VSM4R_VS 0xfe0ff07f +#define MATCH_VSM4R_VV 0xa2082077 +#define MASK_VSM4R_VV 0xfe0ff07f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3348,6 +3355,10 @@ DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS) DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV) DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV) DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV) +/* Zvksed instructions. */ +DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI) +DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS) +DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 77207ea..c378cce 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -421,6 +421,7 @@ enum riscv_insn_class INSN_CLASS_ZVKNHA, INSN_CLASS_ZVKNHB, INSN_CLASS_ZVKNHA_OR_ZVKNHB, + INSN_CLASS_ZVKSED, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, |